请教一下关于CPLD读取DHT22数据的问题
使用的是Altera的EPM240T100C5的板子，程序里面有三个状态
statetest = 1'b0;//for test;
statetest2 = 1'b1;//for test;
为状态测试信号
仿真波显示三个状态都能工作
可是下到板子里面后，DHT22管脚一直是高电平 求解原因
module Dt(
CLK,
RSTn,
IO_port,
data,
dataout,
statetest,statetest2
);
input CLK;
input RSTn;
inout IO_port;
output dataout;
output statetest;
output statetest2;
output data;
reg rdata;
assign data = rdata;
wire CLK_OUT;
Gen_Clk U1(
.CLK(CLK),
.RSTn(RSTn),
.CLK_OUT(CLK_OUT)
);
//tri1 IO_port;
reg rz;
reg rdin;
reg rdout;
wire dout;
assign IO_port=(!rz)?rdin:1'bz;
assign dataout = dout;
assign dout = rdout;
/*if(!z)
din_reg=din; //out
else
dout=dinout; //in
*/
reg State=3'b001;
//
reg count1=10'd0;
reg count2=9'd0;
reg isDone = 1'b0;
reg countd = 8'd0;
reg bitcnt = 6'd0;
reg test;
reg isEn = 1'b0;
reg statetest = 1'b0;
reg statetest2 = 1'b0;
always @ (posedge CLK_OUT )//01号状态，主机发送工作指令
begin
if(State==3'b001)
begin
statetest = 1'b0;//for test;
statetest2 = 1'b1;//for test;
isDone <= 1'b0;
if(count1 < 10'd500)
begin
rz<=1'b0;
if(!rz) rdin=1'b0; //out
count1<=count1+1'b1;
end
else if(count1>=10'd500&&count1<10'd540)
begin
rz<=1'b0;
if(!rz) rdin=1'b1; //out
count1<=count1+1'b1;
end
else if(count1==10'd540)
begin
rz<=1'b1;//gaozu
count1<=0;
State<=3'b010;
end
end
if(State == 3'b010)
begin
statetest = 1'b1;//for test;
statetest2 = 1'b0;//for test;
if(count2 < 9'd160) //0-160读取电平状态 DHT22的两个答应位
begin
rz <= 1'b1;//in
if(rz) rdout = IO_port; //in
count2 <= count2 + 9'd1;
end
else if(count2 == 9'd160)//&&count2<9'd320)
begin
rz <= 1'b1;//in
if(rz) rdout = IO_port; //in
//count2 <= count2 + 9'd1;
count2 <= 9'd0;
//en<=1'b1;
State <= 3'b100; ///////////////////////////////////////
end
/*else if(count2 == 9'd320)
begin
rz <= 1'b1;//in
//if(isDone)
State <= 3'b001;
count2 <= 9'd160; ////////读取完数据置位isDone
end*/
end
if(State == 3'b100)
begin
statetest = 1'b1;//for test;
statetest2 = 1'b1;//for test;
rz <= 1'b1;//in
if(rz) rdout = IO_port; //in
if(countd == 8'd40) begin rdata<=dout; countd<=8'd0;end
if(isEn)countd<=countd+8'd1;
test <= dout;
if((!test)&dout)//posedge
begin
if(bitcnt == 6'd40)begin bitcnt <= 6'd0; isDone <= 1'b1; end //6'd39
else beginbitcnt <= bitcnt + 6'd1; end
isEn <= 1'b1;
end
if(test&(!dout))//negedge
begin
isEn <= 1'b0;
end
if(isDone)begin State <=3'b001; end
end
end
endmodule 代码风格吧。没有else的if多数会被综合成锁存器或者干脆一条线。我可是吃了大亏了，所以我现在每写一个if，都是立刻跟一个else，管它有没有用。 wye11083 发表于 2012-5-10 11:23 static/image/common/back.gif
代码风格吧。没有else的if多数会被综合成锁存器或者干脆一条线。我可是吃了大亏了，所以我现在每写一个if， ...
哦，那我都改改看，改了一上午现在都蒙了，现在连应答都有问题了{:3_55:}
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