求助！！编写的LCD控制器以及testbench仿真时所有信号均为x？ (amobbs.com 阿莫电子技术论坛) -

sorliran1 发表于 2012-5-3 11:46:52

求助！！编写的LCD控制器以及testbench仿真时所有信号均为x？

不知为什么仿真所有的信号都是未知状态！？实在不懂，即便控制模块写的有问题，但clk和rst_n不至于也是未知状态吧??!!请大师们帮忙！！

//////////////控制模块//////
module LCD_Control(
clk,rst_n,
LCD_DATA,LCD_EN,LCD_RW,LCD_RS,LCD_ON,LCD_BLON);

input clk,rst_n;
output LCD_RW,LCD_ON,LCD_BLON;
output LCD_RS;
output LCD_EN;
output LCD_DATA;

reg LCD_RS;
reg LCD_EN;
reg LCD_DATA;
///////////默认信号设置///////////////////////////////
wire LCD_RW=1'b0;//只写
wire LCD_ON=1'b1; //LCD电源开关，置1
wire LCD_BLON=1'b1;
//////////////////主状态机////////////////////////////
parameter IDLE = 2'b01;
parameter A = 2'b10;
///////////////////////////////////////////////////////
reg FF;//任务结束标志位
reg [ 1:0 ] state;
reg [ 4:0 ] LUT_INDEX;
reg [ 7:0 ] cnt_cmd;
reg [ 7:0 ] cnt_data;
parameter LUT_SIZE = 5'd13;
//////////////////tsk_wr_cmd状态//////////////////////
parameter CMD_ST0 = 5'b00001;
parameter CMD_ST1 = 5'b00010;
parameter CMD_ST2 = 5'b00100;
parameter CMD_ST3 = 5'b01000;
parameter CMD_ST4 = 5'b10000;

reg [ 5:0 ] cmd_state;
//////////////tsk_wr_cmd//////////////////////////////
task tsk_wr_cmd;
input [ 7:0 ] cmd_data;
case ( cmd_state )
CMD_ST0: begin
LCD_RS <= 1'b0;
LCD_DATA <= cmd_data;
cmd_state <= CMD_ST1;
end
CMD_ST1: begin
if ( cnt_cmd == 8'd100 ) begin
cnt_cmd <= 8'd0;
cmd_state <= CMD_ST2;
end
else
cnt_cmd <= cnt_cmd + 1;
end
CMD_ST2: begin
LCD_EN <= 1'b1;
cmd_state <= CMD_ST3;
end
CMD_ST3: begin
if ( cnt_cmd == 8'd100 ) begin
cnt_cmd <= 8'd0;
cmd_state <= CMD_ST4;
end
else
cnt_cmd <= cnt_cmd + 1;
end
CMD_ST4: begin
LCD_EN <= 1'b0;
LUT_INDEX <= LUT_INDEX + 1;
FF <= 1'b1; //退出此任务
end
endcase

endtask
//////////////////tsk_wr_data状态/////////////////////
parameter DATA_ST0 = 6'b000001;
parameter DATA_ST1 = 6'b000010;
parameter DATA_ST2 = 6'b000100;
parameter DATA_ST3 = 6'b001000;
parameter DATA_ST4 = 6'b010000;

reg [ 5:0 ] data_state;
////////////////////tsk_wr_data///////////////////////
task tsk_wr_data;
input [ 7:0 ] data;
case ( data_state )
DATA_ST0: begin
LCD_RS <= 1'b1;
LCD_DATA <= data;
data_state <= DATA_ST1;
end
DATA_ST1: begin
if ( cnt_data == 8'd100 ) begin
cnt_data <= 8'd0;
data_state <= DATA_ST2;
end
else
cnt_data <= cnt_data + 1;
end
DATA_ST2: begin
LCD_EN <= 1'b1;
data_state <= DATA_ST3;
end
DATA_ST3: begin
if ( cnt_data == 8'd100 ) begin
cnt_data <= 8'd0;
data_state <= DATA_ST4;
end
else
cnt_data <= cnt_data + 1;
end
DATA_ST4: begin
LCD_EN <= 1'b0;
LUT_INDEX <= LUT_INDEX + 1;
FF <= 1'b1;
end

endcase
endtask
//////////////////////////////////////////////////////
reg [ 7:0 ] LUT_DATA;

/////////////写数据查找表/////////////////////////////
alwaysbegin
case ( LUT_INDEX )
5'd0: LUT_DATA <= 8'h38;
5'd1: LUT_DATA <= 8'h0c;
5'd2: LUT_DATA <= 8'h06;
5'd3: LUT_DATA <= 8'h01;
5'd4: LUT_DATA <= 8'h30;
5'd5: LUT_DATA <= 8'h33;
5'd6: LUT_DATA <= 8'h30;
5'd7: LUT_DATA <= 8'h39;
5'd8: LUT_DATA <= 8'h34;
5'd9: LUT_DATA <= 8'h30;
5'd10: LUT_DATA <= 8'h39;
5'd11: LUT_DATA <= 8'h32;
5'd12: LUT_DATA <= 8'h34;
default: LUT_DATA <= 8'bzzzzzzzz;
endcase
end

////////////////////////////////////////////////////////
always @ ( posedge clk or negedge rst_n )
if ( !rst_n ) begin
cnt_cmd <= 8'd0;
cnt_data <= 8'd0; //计数器初始化
state <= IDLE;
cmd_state <=CMD_ST0;
data_state<= DATA_ST0;
LUT_INDEX <= 5'd0;
FF <= 1'b0;
end
else if ( LUT_INDEX < LUT_SIZE )
case ( state )
IDLE: begin
if ( LUT_INDEX <= 5'd3 ) begin
if ( FF == 1'b0 )
tsk_wr_cmd( LUT_DATA );
else begin
FF <= 1'b0;
state <= IDLE;
end
end
else
state <= A;
end
A: begin
if ( FF == 1'b0 )
tsk_wr_data( LUT_DATA );
else begin
FF <= 1'b0;
state <= A;
end
end
endcase
/////////////////////////////////////////////////////////////////////////

endmodule

下面是testbench
`timescale 1ns/1ns

module t;
reg clk,rst_n;
wire LCD_EN,LCD_RW,LCD_RS,LCD_ON,LCD_BLON;
wire [ 7:0 ] LCD_DATA;

always #5 clk = ~clk;

initial
begin
clk =0;
rst_n=0;
#20;
rst_n=1;
#8000$stop;
end

LCD_Controlt1(.clk(clk),.rst_n(rst_n),.LCD_EN(LCD_EN),.LCD_RW(LCD_RW),.LCD_RS(LCD_RS),.LCD_ON(LCD_ON),.LCD_BLON(LCD_BLON),.LCD_DATA(LCD_DATA));
endmodule

但是不知为什么仿真所有的信号都是未知状态！？实在不懂，即便控制模块写的有问题，但clk和rst_n不至于也是未知状态吧??!!请大师们帮忙！！

fishplj2000 发表于 2012-5-3 13:14:29

是不是simulation的时候开了optimization？

hy2515131 发表于 2012-5-4 09:16:12

LCD的控制器是控制哪个的，详细点可以吗？

hy2515131 发表于 2012-5-4 10:09:09

LCD_Control.v内容如下：
module LCD_Control(
clk,
rst_n,
LCD_DATA,
LCD_EN,
LCD_RW,
LCD_RS,
LCD_ON,
LCD_BLON);

input clk,rst_n;
output LCD_RW,LCD_ON,LCD_BLON;
output LCD_RS;
output LCD_EN;
output LCD_DATA;

reg LCD_RS;
reg LCD_EN;
reg LCD_DATA;
///////////??????///////////////////////////////
//wire LCD_RW=1'b0;//??
//wire LCD_ON=1'b1; //LCD??????1
//wire LCD_BLON=1'b1;

reg LCD_RW=1'b0;//??
reg LCD_ON=1'b1; //LCD??????1
reg LCD_BLON=1'b1;
//////////////////????////////////////////////////
parameter IDLE = 2'b01;
parameter A = 2'b10;
///////////////////////////////////////////////////////
reg FF;//???????
reg [ 1:0 ] state;
reg [ 4:0 ] LUT_INDEX;
reg [ 7:0 ] cnt_cmd;
reg [ 7:0 ] cnt_data;
parameter LUT_SIZE = 5'd13;
//////////////////tsk_wr_cmd??//////////////////////
parameter CMD_ST0 = 5'b00001;
parameter CMD_ST1 = 5'b00010;
parameter CMD_ST2 = 5'b00100;
parameter CMD_ST3 = 5'b01000;
parameter CMD_ST4 = 5'b10000;

reg [ 5:0 ] cmd_state;
//////////////tsk_wr_cmd//////////////////////////////
task tsk_wr_cmd;
input [ 7:0 ] cmd_data;
case ( cmd_state )
CMD_ST0: begin
LCD_RS <= 1'b0;
LCD_DATA <= cmd_data;
cmd_state <= CMD_ST1;
end
CMD_ST1: begin
if ( cnt_cmd == 8'd100 ) begin
cnt_cmd <= 8'd0;
cmd_state <= CMD_ST2;
end
else
cnt_cmd <= cnt_cmd + 1;
end
CMD_ST2: begin
LCD_EN <= 1'b1;
cmd_state <= CMD_ST3;
end
CMD_ST3: begin
if ( cnt_cmd == 8'd100 ) begin
cnt_cmd <= 8'd0;
cmd_state <= CMD_ST4;
end
else
cnt_cmd <= cnt_cmd + 1;
end
CMD_ST4: begin
LCD_EN <= 1'b0;
LUT_INDEX <= LUT_INDEX + 1;
FF <= 1'b1; //?????
end
endcase

endtask
//////////////////tsk_wr_data??/////////////////////
parameter DATA_ST0 = 6'b000001;
parameter DATA_ST1 = 6'b000010;
parameter DATA_ST2 = 6'b000100;
parameter DATA_ST3 = 6'b001000;
parameter DATA_ST4 = 6'b010000;

reg [ 5:0 ] data_state;

////////////////////tsk_wr_data///////////////////////
task tsk_wr_data;
input [ 7:0 ] data;
case ( data_state )
DATA_ST0: begin
LCD_RS <= 1'b1;
LCD_DATA <= data;
data_state <= DATA_ST1;
end
DATA_ST1: begin
if ( cnt_data == 8'd100 ) begin
cnt_data <= 8'd0;
data_state <= DATA_ST2;
end
else
cnt_data <= cnt_data + 1;
end
DATA_ST2: begin
LCD_EN <= 1'b1;
data_state <= DATA_ST3;
end
DATA_ST3: begin
if ( cnt_data == 8'd100 ) begin
cnt_data <= 8'd0;
data_state <= DATA_ST4;
end
else
cnt_data <= cnt_data + 1;
end
DATA_ST4: begin
LCD_EN <= 1'b0;
LUT_INDEX <= LUT_INDEX + 1;
FF <= 1'b1;
end

endcase
endtask

//////////////////////////////////////////////////////
reg [ 7:0 ] LUT_DATA;

/////////////??????/////////////////////////////
always @ ( posedge clk or negedge rst_n )

begin
case ( LUT_INDEX )
5'd0: LUT_DATA <= 8'h38;
5'd1: LUT_DATA <= 8'h0c;
5'd2: LUT_DATA <= 8'h06;
5'd3: LUT_DATA <= 8'h01;
5'd4: LUT_DATA <= 8'h30;
5'd5: LUT_DATA <= 8'h33;
5'd6: LUT_DATA <= 8'h30;
5'd7: LUT_DATA <= 8'h39;
5'd8: LUT_DATA <= 8'h34;
5'd9: LUT_DATA <= 8'h30;
5'd10: LUT_DATA <= 8'h39;
5'd11: LUT_DATA <= 8'h32;
5'd12: LUT_DATA <= 8'h34;
default: LUT_DATA <= 8'bzzzzzzzz;
endcase
end

////////////////////////////////////////////////////////
always @ ( posedge clk or negedge rst_n )
if ( !rst_n )
begin
cnt_cmd <= 8'd0;
cnt_data <= 8'd0; //??????
state <= IDLE;
cmd_state <=CMD_ST0;
data_state<= DATA_ST0;
LUT_INDEX <= 5'd0;
FF <= 1'b0;
end
else if ( LUT_INDEX < LUT_SIZE )
case ( state )
IDLE: begin
if ( LUT_INDEX <= 5'd3 ) begin
if ( FF == 1'b0 )
tsk_wr_cmd( LUT_DATA );
else begin
FF <= 1'b0;
state <= IDLE;
end
end
else
state <= A;
end
A: begin
if ( FF == 1'b0 )
tsk_wr_data( LUT_DATA );
else begin
FF <= 1'b0;
state <= A;
end
end
endcase

/////////////////////////////////////////////////////////////////////////

endmodule

hy2515131 发表于 2012-5-4 10:11:17

testbench文件如下:
LCD_ControlTest.v

`timescale 1ns/1ns

moduleLCD_ControlTest;
reg clk,rst_n;
wire LCD_EN,LCD_RW,LCD_RS,LCD_ON,LCD_BLON;
wire [ 7:0 ] LCD_DATA;

LCD_ControlTest(
.clk(clk),
.rst_n(rst_n),
.LCD_EN(LCD_EN),
.LCD_RW(LCD_RW),
.LCD_RS(LCD_RS),
.LCD_ON(LCD_ON),
.LCD_BLON(LCD_BLON),
.LCD_DATA(LCD_DATA)
);

always #1 clk = ~clk;

initial
begin
clk =0;
rst_n=0;
#20;
rst_n=1;
#4000
$stop;
end

endmodule

hy2515131 发表于 2012-5-4 10:11:49

波形图见附件javascript:;

hy2515131 发表于 2012-5-4 10:12:46

你有一个always语句没有检测条件，我记得是这样，你测试一下。

wye11083 发表于 2012-5-4 10:12:50

我看你这仿真没跑吧。你要点执行，让仿真器往后跑一段。

hy2515131 发表于 2012-5-4 12:12:07

wye11083 发表于 2012-5-4 10:12 static/image/common/back.gif
我看你这仿真没跑吧。你要点执行，让仿真器往后跑一段。

不是没有执行，而是代码的问题，有一条always没有处理。

wye11083 发表于 2012-5-4 16:18:59

hy2515131 发表于 2012-5-4 12:12 static/image/common/back.gif
不是没有执行，而是代码的问题，有一条always没有处理。

我说的是LZ的波形图。你看他的波形图确实是定在0ps的，也就是说LZ根本就没有仿真。

hy2515131 发表于 2012-5-4 16:25:54

我测试过了，仿真了就是没有波形，原因是他的代码的问题。

hy2515131 发表于 2012-5-4 16:26:33

已经改正了！

sorliran1 发表于 2012-5-6 12:23:17

hy2515131 发表于 2012-5-4 16:26 static/image/common/back.gif
已经改正了！

谢谢，看到了，呵呵

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求助！！编写的LCD控制器以及testbench仿真时所有信号均为x？