U盘控制器设计中，返回数据与状态响应的问题
我的程序中设计顺序为 1FPGA 读PC发来的INQUIRY 指令， 2写 INQUIRY信息 3 返回状态
上图的结果却是2和3的顺序反了，找不到原因。附上程序，求大神帮忙解析，
module ufi_if(
clk,
read_n,
write_n,
rst_n,
empty_n,
full_n,
data_i,
data_o,
addr_i,
pktend_n,
fifoadr
);
reg clk_2;
reg clk_4;
reg clk_8;
always@(posedge clk)
clk_2<=~clk_2;
always@(posedge clk_2)
clk_4<=~clk_4;
always@(posedge clk_4)
clk_8<=~clk_8;
input clk;
input rst_n;
input empty_n;
input full_n;
input addr_i;
input data_i;
output reg fifoadr;
output reg data_o;
output reg read_n;
output reg write_n;
output reg pktend_n;
/////////////////////////////////////memory and state
reg state,next,temp;
reg CBW;
parameter start=10'b0000000001;
parameter read_1=10'b0000000010;
parameter write_1=10'b0000000100;
parameter write_2=10'b0000001000;
parameter state_1=10'b0000010000;
parameter state_2=10'b0000100000;
parameter pktend_1=10'b0001000000;
parameter pktend_2=10'b0010000000;
parameter pktend_3=10'b0100000000;
parameter pktend_4=10'b1000000000;
reg i=6'h00;
reg j=4'h0;
reg SCSI_INQUIRY;
always@(posedge clk_8)
begin
SCSI_INQUIRY=8'h00;
SCSI_INQUIRY=8'h80;
SCSI_INQUIRY=8'h00;
SCSI_INQUIRY=8'h01;
SCSI_INQUIRY=8'h1f;
SCSI_INQUIRY=8'h00;
SCSI_INQUIRY=8'h00;
SCSI_INQUIRY=8'h00;
SCSI_INQUIRY=8'h20;
SCSI_INQUIRY=8'h20;
SCSI_INQUIRY=8'h20;
SCSI_INQUIRY=8'h20;
SCSI_INQUIRY=8'h20;
SCSI_INQUIRY=8'h20;
SCSI_INQUIRY=8'h20;
SCSI_INQUIRY=8'h20;
SCSI_INQUIRY=8'h56;
SCSI_INQUIRY=8'h69;
SCSI_INQUIRY=8'h72;
SCSI_INQUIRY=8'h69;
SCSI_INQUIRY=8'h64;
SCSI_INQUIRY=8'h69;
SCSI_INQUIRY=8'h73;
SCSI_INQUIRY=8'h20;
SCSI_INQUIRY=8'h4f;
SCSI_INQUIRY=8'h50;
SCSI_INQUIRY=8'h54;
SCSI_INQUIRY=8'h4f;
SCSI_INQUIRY=8'h20;
SCSI_INQUIRY=8'h32;
SCSI_INQUIRY=8'h2e;
SCSI_INQUIRY=8'h30;
end
reg CSW;
/////////////////////////////////
reg read_nd;
always@(posedge clk_8)
read_n<=read_nd;
reg write_nd;
always@(posedge clk_8)
write_n<=write_nd;
reg empty_nr;
always@(posedge clk_8)
empty_nr<=empty_n;
reg full_nr;
always@(posedge clk_8)
full_nr<=full_n;
reg data_i_r;
always@(posedge clk_8)
data_i_r<=data_i;
reg pktend_nd;
always@(posedge clk_8)
pktend_n<=pktend_nd;
reg addr_i_r;
always@(posedge clk_8)
addr_i_r<=addr_i;
reg data_o_d;
always@(posedge clk_8)
data_o_d_d<=data_o_d;
reg data_o_d_d;
always@(posedge clk_8)
data_o<=data_o_d_d;
reg fifoadr_d;
always@(posedge clk_8)
fifoadr<=fifoadr_d;
reg empty_flag;
always@(empty_nr)
if(empty_nr)
empty_flag<=1'b0;
else
empty_flag<=1'b1;
always@(posedge clk_8,negedge rst_n)
if(!rst_n)
begin
write_nd<=1'b1;
read_nd<=1'b1;
pktend_nd<=1'b1;
fifoadr_d<=2'b11;
i<='b0;
j<='b0;
end
else
begin
pktend_nd<=1'b0;
state=next;
case (state)
start: //first step
begin
if(empty_flag)
next<=start;
else
begin
fifoadr_d<=2'b00;
read_nd<=1'b0;
next<=read_1;
end
end
read_1:
begin
CBW<=data_i_r;
if(addr_i_r<8'h08)
CSW=CBW;
if(!empty_flag)
next<=read_1;
else
begin
read_nd<=1'b1;
fifoadr_d<=2'b10;
next<=write_1;
end
end
write_1:
begin
write_nd<=1'b0;//
if(CBW!=8'h12)
next<=write_1;
else if(full_nr&i!=32)
begin
data_o_d=SCSI_INQUIRY;
i<=i+1'b1;
next<=write_2;
end
else
begin
i<=0;
j<=0;
write_nd<=1'b1;
temp<=state_1;
next<=pktend_1;
end
end
write_2:
begin
next<=write_1;
end
pktend_1:
begin
next<=pktend_2;
end
pktend_2:
begin
next<=pktend_3;
end
pktend_3:
begin
pktend_nd<=1'b1;//
if(full_nr)
next<=pktend_4;
else
next<=pktend_1;
end
pktend_4:
begin
pktend_nd<=1'b0;
next<=temp;
end
state_1:
begin
pktend_nd<=1'b0;
write_nd<=1'b0;
fifoadr_d<=2'b10;
if(j!=13)
begin
if(j<8)
data_o_d=CSW;
else
data_o_d<=8'b00;
j<=j+1'b1;
next<=state_2;
end
else
begin
write_nd<=1'b1;
temp<=start;
next<=pktend_1;
end
end
state_2:
begin
next<=state_1;
end
default:
begin
next<=start;
write_nd<=1'b1;
read_nd<=1'b1;
end
endcase
end
endmodule
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