FPGA读68013 fifo问题
本帖最后由 yp19890718 于 2012-4-17 17:27 编辑用Singal tap可以看到如此现象；
再还未激活SLOE和SLRD读取的信号时，FD就有信号，此信号是OUT端数据包的第一个字（16位），空标志是“假”。一旦我按下复位键开始进入读取状态，即激活SLRD与SLOE，FD就变成了0XFFFF，空标志变成“真”，不晓得为什么？就读不了了。
求大神指点。
void TD_Init(void) // Called once at startup
{
// set the CPU clock to 48MHz
CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1); //48M
IFCONFIG |= 0x0B;//异步，从FIFO模式.
PORTACFG|=0X00; //不需要SLCS
FIFOPINPOLAR = 0x00; // set all slave FIFO interface pins as active low PKTEND OR SLOE SLWR LOW AVTIVE
SYNCDELAY;
REVCTL = 0x00; // enable the external master
SYNCDELAY;
// config the endpoints direction
EP1OUTCFG = 0xA0;//enable and bulk type
EP1INCFG = 0xA0;
SYNCDELAY; // see TRM section 15.14
EP8CFG = 0x60;
SYNCDELAY;
EP4CFG = 0x20;
SYNCDELAY;
EP6CFG = 0xe2;//enable IN bulk 512 DOUBLE buffer
SYNCDELAY;
EP2CFG = 0xA2;
SYNCDELAY;
PINFLAGSAB = 0xe8;// FLAGA - fixed EP2EF, FLAGB - fixed EP6FF
SYNCDELAY; //FLAGA引脚，EP2空时为0,非空为1,FLAGB引脚，EP6满为0，非满为1
//-------------------------
INPKTEND = 0x06;
SYNCDELAY;
INPKTEND = 0x06;
SYNCDELAY;
OUTPKTEND = 0x82;
SYNCDELAY;
OUTPKTEND = 0x82;
SYNCDELAY;
EP2BCL = 0x80; // arm EP2OUT by writing byte count w/skip.
SYNCDELAY;
EP2BCL = 0x80;
SYNCDELAY;
EP2FIFOCFG = 0x01;
SYNCDELAY;
EP2FIFOCFG = 0x11;//EP2 IS AUTOOUT=1 AUTOIN =0 ZEROLEN=0 WORDIDE=1 配置EP6自动方式16位总
SYNCDELAY;
//config the endpoint6
EP6FIFOCFG = 0x0D;//EP6 IS AUTOOUT=0 AUTOIN =1 ZEROLEN=1 WORDIDE=1 配置EP6自动方式16位总
SYNCDELAY;
//----------------------------------------
EP6AUTOINLENH = 0x02; //set the packet size 512
SYNCDELAY;
EP6AUTOINLENL = 0x00;
SYNCDELAY;
// arm EP2OUT by writing byte count w/skip.
// SYNCDELAY;
// since the defaults are double buffered we must write dummy byte counts twice
//SYNCDELAY;
SYNCDELAY;
AUTOPTRSETUP|=0X03;
}
void TD_Poll(void) // Called repeatedly while the device is idle
{
EP2BCL=0X80;
SYNCDELAY;
EP2BCL=0X80;
SYNCDELAY;
}
//////////////////////////////////////////////
FPGA代码
module test(
fd,slrd,empty,sloe,fifoadr,clk,rst,
ram,slcs
);
input fd;
output reg slrd;
output reg sloe;
output reg fifoadr;
input empty;
input clk;
input rst;
output reg ram;
output reg slcs;
reg state,next;
parameter s1=2'b00;
parameter s2=2'b01;
parameter s3=2'b11;
parameter s4=2'b10;
always@(posedge clk,negedge rst)
if(!rst)
state<=s1;
else
case (state)
s1:
begin
fifoadr<=2'b00;
state<=s2;
end
s2:
begin
if(empty)
state<=s3;
else
state<=s2;
end
s3:
begin
sloe<=0;
slrd<=0;
ram<=fd;
state<=s4;
end
s4:
begin
sloe<=1;
slrd<=1;
if(empty)
state<=s2;
else
state<=s1;
end
endcase
endmodule
页:
[1]