LGT8F0XA头文件 FOR IARAVR
本帖最后由 uc_c++ 于 2012-4-16 16:41 编辑LGT8F0XA头文件 FOR IARAVR
先贴部分。#ifndef __IAR_SFR_DEF_MACRO__
#define __IAR_SFR_DEF_MACRO__
#define IAR_SFR_B_RSFR_B_R
#define IAR_SFR_W_RSFR_W_R
#define IAR_SFR_B_N(_ADDR, _NAME, _B7, _B6, _B5, _B4, _B3, _B2, _B1, _B0)\
SFR_B_N(_ADDR, _NAME, _B7, _B6, _B5, _B4, _B3, _B2, _B1, _B0)\
enum\
{\
MASK_##_B7=(1U<<7),\
MASK_##_B6=(1U<<6),\
MASK_##_B5=(1U<<5),\
MASK_##_B4=(1U<<4),\
MASK_##_B3=(1U<<5),\
MASK_##_B2=(1U<<2),\
MASK_##_B1=(1U<<1),\
MASK_##_B0=(1U<<0),\
}; \
enum\
{\
_B7=(7),\
_B6=(6),\
_B5=(5),\
_B4=(4),\
_B3=(5),\
_B2=(2),\
_B1=(1),\
_B0=(0),\
};
#endif
IAR_SFR_B_R(0xF6, DEVID3)
IAR_SFR_B_R(0xF5, DEVID2)
IAR_SFR_B_R(0xF4, DEVID1)
IAR_SFR_B_R(0xF3, DEVID0)
IAR_SFR_B_N(0xF2, PMCR,PMCR_Dummy7,LFEN,EXTMSE,CFDS,PMCR_Dummy3,OSCMEN,RC1KEN,RC16MEN)
IAR_SFR_B_R(0xD7, RTCNTH)
IAR_SFR_B_R(0xD6, RTCNTM)
IAR_SFR_B_R(0xD5, RTCNTL)
IAR_SFR_B_R(0xD4, RTCTOPH)
IAR_SFR_B_R(0xD3, RTCTOPM)
IAR_SFR_B_R(0xD2, RTCTOPL)
IAR_SFR_B_R(0xD1, RTCISR)
IAR_SFR_B_R(0xD0, RTCSR)例子：
#include "iolgt8f08a.h"
int main()
{
PMCR |=1<<RC16MEN;
PMCR |=MASK_RC16MEN;
PMCR_RC16MEN=1;
PMCR_Bit0=1;
PMCR &=~(1<<RC16MEN);
PMCR &=~MASK_RC16MEN;
PMCR_RC16MEN=0;
PMCR_Bit0=0;
PMCR ^=1<<RC16MEN;
PMCR ^=MASK_RC16MEN;
PMCR_RC16MEN=!PMCR_RC16MEN;
PMCR_Bit0=!PMCR_Bit0;
if(PMCR & (1<<RC16MEN))
{
}
if(PMCR & MASK_RC16MEN)
{
}
if(PMCR_RC16MEN!=0)
{
}
if(PMCR_Bit0!=0)
{
}
while(1);
}
本帖最后由 uc_c++ 于 2012-4-16 16:44 编辑
完整的头文件，不保证完全正确。
#ifdef__IAR_SYSTEMS_ICC__
#ifndef _SYSTEM_BUILD
#pragma system_include
#endif
#endif
#include "iomacro.h"
#if TID_GUARD(3)
//#error This file should only be compiled with iccavr or aavr with processor option -v3
#endif /* TID_GUARD(3) */
#ifdef __HAS_RAMPZ__
#error This file should not have RAMPZ enabled, use --cpu or --64k_flash
#endif /* __HAS_RAMPZ__ */
#ifndef __IOLGT8F0XA_H__
/* SFRs are local in assembler modules (so this file may need to be */
/* included in more than one module in the same source file), */
/* but #defines must only be made once per source file. */
/*==============================*/
/* Interrupt Vector Definitions */
/*==============================*/
/* NB! vectors are specified as byte addresses */
#define RESET_vect (0x00) /* External Pin, Power-on Reset, Brown-out Reset,
Watchdog Reset, and JTAG AVR Reset */
#define INT0_vect (0x04) /* External Interrupt Request 0 */
#define INT1_vect (0x08) /* External Interrupt Request 1 */
#define INT2_vect (0x0C) /* External Interrupt Request 2 */
#define PCINT0_vect (0x10) /* Pin Change Interrupt Request 0 */
#define PCINT1_vect (0x14) /* Pin Change Interrupt Request 1 */
#define PCINT2_vect (0x18) /* Pin Change Interrupt Request 2 */
#define PCINT3_vect (0x1C) /* Pin Change Interrupt Request 3 */
#define WDT_vect (0x20) /* Watchdog Time-out Interrupt */
#define TIMER2_COMPA_vect (0x24) /* Timer/Counter2 Compare Match A */
#define TIMER2_COMPB_vect (0x28) /* Timer/Counter2 Compare Match B */
#define TIMER2_OVF_vect (0x2C) /* Timer/Counter2 Overflow */
#define TIMER1_CAPT_vect (0x30) /* Timer/Counter1 Capture Event */
#define TIMER1_COMPA_vect (0x34) /* Timer/Counter1 Compare Match A */
#define TIMER1_COMPB_vect (0x38) /* Timer/Counter1 Compare Match B */
#define TIMER1_OVF_vect (0x3C) /* Timer/Counter1 Overflow */
#define TIMER0_COMPA_vect (0x40) /* Timer/Counter0 Compare Match A */
#define TIMER0_COMPB_vect (0x44) /* Timer/Counter0 Compare match B */
#define TIMER0_OVF_vect (0x48) /* Timer/Counter0 Overflow */
#define SPI_STC_vect (0x4C) /* SPI Serial Transfer Complete */
#define USART0_RX_vect (0x50) /* USART0 Rx Complete */
#define USART0_UDRE_vect (0x54) /* USART0 Data Register Empty */
#define USART0_TX_vect (0x58) /* USART0 Tx Complete */
#define ANALOG_COMP_vect (0x5C) /* Analog Comparator */
#define ADC_vect (0x60) /* ADC Conversion Complete */
#define EE_READY_vect (0x64) /* EEPROM Ready */
#define TWI_vect (0x68) /* 2-wire Serial Interface */
#define SPM_READY_vect (0x6C) /* Store Program Memory Ready */
#define USART1_RX_vect (0x70) /* USART1 Rx Complete */
#define USART1_UDRE_vect (0x74) /* USART1 Data Register Empty */
#define USART1_TX_vect (0x78) /* USART1 Tx Complete */
#define RTC_vect (0X8C)
#endif /* __IOLGT8F0XA_H__ (define part) */
/* Include the SFR part if this file has not been included before,
* OR this file is included by the assembler (SFRs must be defined in
* each assembler module). */
#if !defined(__IOLGT8F0XA_H__) || defined(__IAR_SYSTEMS_ASM__)
#define __IOLGT8F0XA_H__
#pragma language=save
#pragma language=extended
/*==========================*/
/* Predefined SFR Addresses */
/*==========================*/
/****************************************************************************
* An example showing the SFR_B() macro call,
* the expanded result and usage of this result:
*
* IAR_SFR_B_R(0x1F, AVR) Expands to:
* __io union {
* unsigned char AVR; // The sfrb as 1 byte
* struct { // The sfrb as 8 bits
* unsigned char AVR_Bit0:1,
* AVR_Bit1:1,
* AVR_Bit2:1,
* AVR_Bit3:1,
* AVR_Bit4:1,
* AVR_Bit5:1,
* AVR_Bit6:1,
* AVR_Bit7:1;
* };
* } @ 0x1F;
* Examples of how to use the expanded result:
* AVR |= (1<<5);
* or like this:
* AVR_Bit5 = 1;
*
*
*
* An example showing the IAR_SFR_B_N() macro call,
* the expanded result and usage of this result:
* IAR_SFR_B_N(0x25,TCCR2, FOC2, WGM20, COM21, COM20, WGM21, CS22, CS21, CS20)
*Expands to:
*__io union {
* unsigned char TCCR2;
* struct {
* unsigned char TCCR2_Bit0:1,
* TCCR2_Bit1:1,
* TCCR2_Bit2:1,
* TCCR2_Bit3:1,
* TCCR2_Bit4:1,
* TCCR2_Bit5:1,
* TCCR2_Bit6:1,
* TCCR2_Bit7:1;
* };
* struct {
* unsigned char TCCR2_CS20:1,
* TCCR2_CS21:1,
* TCCR2_CS22:1,
* TCCR2_WGM21:1,
* TCCR2_COM20:1,
* TCCR2_COM21:1,
* TCCR2_WGM20:1,
* TCCR2_FOC2:1;
* };
* } @ 0x25;
* Examples of how to use the expanded result:
* TCCR2 |= (1<<5);
* or if ENABLE_BIT_DEFINITIONS is defined
* TCCR2 |= (1<<COM21);
* or like this:
* TCCR2_Bit5 = 1;
* or like this:
* TCCR2_COM21 = 1;
***************************************************************************/
#ifndef __IAR_SFR_DEF_MACRO__
#define __IAR_SFR_DEF_MACRO__
#define IAR_SFR_B_RSFR_B_R
#define IAR_SFR_W_RSFR_W_R
#define IAR_SFR_B_N(_ADDR, _NAME, _B7, _B6, _B5, _B4, _B3, _B2, _B1, _B0)\
SFR_B_N(_ADDR, _NAME, _B7, _B6, _B5, _B4, _B3, _B2, _B1, _B0)\
enum\
{\
MASK_##_B7=(1U<<7),\
MASK_##_B6=(1U<<6),\
MASK_##_B5=(1U<<5),\
MASK_##_B4=(1U<<4),\
MASK_##_B3=(1U<<5),\
MASK_##_B2=(1U<<2),\
MASK_##_B1=(1U<<1),\
MASK_##_B0=(1U<<0),\
}; \
enum\
{\
_B7=(7),\
_B6=(6),\
_B5=(5),\
_B4=(4),\
_B3=(5),\
_B2=(2),\
_B1=(1),\
_B0=(0),\
};
#endif
IAR_SFR_B_R(0xF6, DEVID3)
IAR_SFR_B_R(0xF5, DEVID2)
IAR_SFR_B_R(0xF4, DEVID1)
IAR_SFR_B_R(0xF3, DEVID0)
IAR_SFR_B_N(0xF2, PMCR,PMCR_Dummy7,LFEN,EXTMSE,CFDS,PMCR_Dummy3,OSCMEN,RC1KEN,RC16MEN)
IAR_SFR_B_R(0xD7, RTCNTH)
IAR_SFR_B_R(0xD6, RTCNTM)
IAR_SFR_B_R(0xD5, RTCNTL)
IAR_SFR_B_R(0xD4, RTCTOPH)
IAR_SFR_B_R(0xD3, RTCTOPM)
IAR_SFR_B_R(0xD2, RTCTOPL)
IAR_SFR_B_R(0xD1, RTCISR)
IAR_SFR_B_R(0xD0, RTCSR)
IAR_SFR_B_R(0xC6, UDR0)
IAR_SFR_W_R(0xC4, UBRR0)
IAR_SFR_B_N(0xC2, UCSR0C, UMSEL01, UMSEL00, UPM01, UPM00, USBS0, UCSZ01, UCSZ00, UCPOL0)
IAR_SFR_B_N(0xC1, UCSR0B, RXCIE0, TXCIE0, UDRIE0, RXEN0, TXEN0, UCSZ02, RXB80, TXB80)
IAR_SFR_B_N(0xC0, UCSR0A, RXC0, TXC0, UDRE0, FE0, DOR0, UPE0, U2X0, MPCM0)
SFR_W_R(0x8A, OCR1B)
SFR_W_R(0x88, OCR1A)
SFR_W_R(0x86, ICR1)
SFR_W_R(0x84, TCNT1)
IAR_SFR_B_N(0x82, TCCR1C, FOC1A, FOC1B, TCCR1C_Dummy5, TCCR1C_Dummy4, TCCR1C_Dummy3, TCCR1C_Dummy2, TCCR1C_Dummy1, TCCR1C_Dummy0)
IAR_SFR_B_N(0x81, TCCR1B, ICNC1, ICES1, TCCR1B_Dummy5, WGM13, WGM12, CS12, CS11, CS10)
IAR_SFR_B_N(0x80, TCCR1A, COM1A1, COM1A0, COM1B1, COM1B0, TCCR1B_Dummy3, TCCR1B_Dummy2, WGM11, WGM10)
IAR_SFR_B_N(0x7E, DIDR0, ADC7D, ADC6D, ADC5D, ADC4D, ADC3D, ADC2D, ADC1D, ADC0D)
IAR_SFR_B_N(0x7D, ADTM,ADTM_Dummy7,ADTM_Dummy6,ADTM_Dummy5,ADTM_Dummy4,ADTM_Dummy3,ADCTM2,ADCTM1,ADCTM0) //LGT
IAR_SFR_B_N(0x7C, ADMUX, REFSX1, REFSX0, ADLAR, CHMUX4, CHMUX3, CHMUX2, CHMUX1, CHMUX0)//LTG
IAR_SFR_B_N(0x7B, ADCSRB, ADCSRB_Dummy7, ACME, ADICTL, ADGAIN1, ADGAIN0, ADTSX2, ADTSX1, ADTSX0)//LGT
IAR_SFR_B_N(0x7A, ADCSRA, ADEN, ADSC, ADATE, ADIF, ADIE, ADPS2, ADPSX1, ADPSX0)
SFR_W_R(0x78, ADC)
IAR_SFR_B_N(0x73, PCMSK3, PCINT31, PCINT30, PCINT29, PCINT28, PCINT27, PCINT26, PCINT25, PCINT24)
IAR_SFR_B_N(0x6F, TIMSK1, TIMSK1_Dummy7, TIMSK1_Dummy6, ICIE1, TIMSK1_Dummy4, TIMSK1_Dummy3, OCIE1B, OCIE1A, TOIE1)
IAR_SFR_B_N(0x6E, TIMSK0, TIMSK0_Dummy7, TIMSK0_Dummy6, TIMSK0_Dummy5, TIMSK0_Dummy4, TIMSK0_Dummy3, OCIE0B, OCIE0A, TOIE0)
IAR_SFR_B_N(0x6D, PCMSK2, PCINT23, PCINT22, PCINT21, PCINT20, PCINT19, PCINT18, PCINT17, PCINT16)
IAR_SFR_B_N(0x6C, PCMSK1, PCINT15, PCINT14, PCINT13, PCINT12, PCINT11, PCINT10, PCINT9, PCINT8)
IAR_SFR_B_N(0x6B, PCMSK0, PCINT7, PCINT6, PCINT5, PCINT4, PCINT3, PCINT2, PCINT1, PCINT0)
IAR_SFR_B_N(0x69, EICRA, EICRA_Dummy7, EICRA_Dummy6, ISC21, ISC20, ISC11, ISC10, ISC01, ISC00)
IAR_SFR_B_N(0x68, PCICR, PCICR_Dummy7, PCICR_Dummy6, PCICR_Dummy5, PCICR_Dummy4, PCIE3, PCIE2, PCIE1, PCIE0)
IAR_SFR_B_R(0x66, OSCCAL)
IAR_SFR_B_N(0x64, PRR0, PRR0_Dummy7, PRR0_Dummy6, PRTIM0, PRR0_Dummy4, PRTIM1, PRR0_Dummy2, PRUSART0, PRADC) //LGT
IAR_SFR_B_N(0x61, CLKPR, CLKPCE, CLKPR_Dummy6, CLKPR_Dummy5, CLKPR_Dummy4, CLKPS3, CLKPS2, CLKPS1, CLKPS0)
IAR_SFR_B_N(0x60, WDTCSR, WDIF, WDIE, WDP3, WDCE, WDE, WDP2, WDP1, WDP0)
IAR_SFR_B_N(0x3F, SREG, I, T, H, S, V, N, Z, C)
SFR_W_N(0x3D, SP, SP15, SP14, SP13, SP12, SP11, SP10, SP9, SP8, SP7, SP6, SP5, SP4, SP3, SP2, SP1, SP0)
IAR_SFR_B_N(0x35, MCUCR, SWDD, MCUCR_Dummy6, MCUCR_Dummy5, PUD, MCUCR_Dummy3, MCUCR_Dummy2, IVSEL, IVCE)
IAR_SFR_B_N(0x34, MCUSR, MCUSR_Dummy7, MCUSR_Dummy6, SWRF, OCDRF, WDRF, BORF, EXTRF, PORF)//LGT
IAR_SFR_B_N(0x33, SMCR, SMCR_Dummy7, SMCR_Dummy6, SMCR_Dummy5, SMCR_Dummy4, SMOD2, SMOD1, SMOD0, SE)//LGT
IAR_SFR_B_N(0x30, ACSR, ACD, ACBG, ACO, ACI, ACIE, ACIC, ACIS1, ACIS0)
IAR_SFR_B_R(0x2B, GPIOR2)
IAR_SFR_B_R(0x2A, GPIOR1)
IAR_SFR_B_R(0x29, EEDRH) //LGT
IAR_SFR_B_R(0x27, OCR0)
IAR_SFR_B_R(0x26, TCNT0)
IAR_SFR_B_N(0x25, TCCR0B, FOC0A, FOC0B, TCCR0B_Dummy5, TCCR0B_Dummy4, WGM02, CS02, CS01, CS00)
IAR_SFR_B_N(0x24, TCCR0A, COM0A1, COM0A0, COM0B1, COM0B0, TCCR0A_Dummy3, TCCR0A_Dummy2, WGM01, WGM00)
IAR_SFR_B_N(0x23, GTCCR, PSR10, GTCCR_Dummy6, GTCCR_Dummy5, GTCCR_Dummy4, GTCCR_Dummy3, GTCCR_Dummy2, GTCCR_Dummy1, TSM)//LGT
SFR_W_R(0x21, EEAR)
IAR_SFR_B_R(0x20, EEDR)
IAR_SFR_B_N(0x1F, EECR, EEPEN, EECR_Dummy6, EEPM1, EEPM0, EERIE, EEMWE, EEWE, EERE)
IAR_SFR_B_R(0x1E, GPIOR0)
IAR_SFR_B_N(0x1D, EIMSK, EIMSK_Dummy7, EIMSK_Dummy6, EIMSK_Dummy5, EIMSK_Dummy4, EIMSK_Dummy3, INT2, INT1, INT0)
IAR_SFR_B_N(0x1C, EIFR, EIFR_Dummy7, EIFR_Dummy6, EIFR_Dummy5, EIFR_Dummy4, EIFR_Dummy3, INTF2, INTF1, INTF0)
IAR_SFR_B_N(0x1B, PCIFR, PCIFR_Dummy7, PCIFR_Dummy6, PCIFR_Dummy5, PCIFR_Dummy4, PCIF3, PCIF2, PCIF1, PCIF0)
IAR_SFR_B_N(0x16, TIFR1, TIFR1_Dummy7, TIFR1_Dummy6, ICF1, TIFR1_Dummy4, TIFR1_Dummy3, OCF1B, OCF1A, TOV1)
IAR_SFR_B_N(0x15, TIFR0, TIFR0_Dummy7, TIFR0_Dummy6, TIFR0_Dummy5, TIFR0_Dummy4, TIFR0_Dummy3, OCF0B, OCF0A, TOV0)
IAR_SFR_B_N(0x0B, PORTD, PORTD7, PORTD6, PORTD5, PORTD4, PORTD3, PORTD2, PORTD1, PORTD0)
IAR_SFR_B_N(0x0A, DDRD, DDD7, DDD6, DDD5, DDD4, DDD3, DDD2, DDD1, DDD0)
IAR_SFR_B_N(0x09, PIND, PIND7, PIND6, PIND5, PIND4, PIND3, PIND2, PIND1, PIND0)
IAR_SFR_B_N(0x08, PORTC, PORTC7, PORTC6, PORTC5, PORTC4, PORTC3, PORTC2, PORTC1, PORTC0)
IAR_SFR_B_N(0x07, DDRC, DDC7, DDC6, DDC5, DDC4, DDC3, DDC2, DDC1, DDC0)
IAR_SFR_B_N(0x06, PINC, PINC7, PINC6, PINC5, PINC4, PINC3, PINC2, PINC1, PINC0)
IAR_SFR_B_N(0x05, PORTB, PORTB7, PORTB6, PORTB5, PORTB4, PORTB3, PORTB2, PORTB1, PORTB0)
IAR_SFR_B_N(0x04, DDRB, DDB7, DDB6, DDB5, DDB4, DDB3, DDB2, DDB1, DDB0)
IAR_SFR_B_N(0x03, PINB, PINB7, PINB6, PINB5, PINB4, PINB3, PINB2, PINB1, PINB0)
IAR_SFR_B_N(0x02, PORTA, PORTA7, PORTA6, PORTA5, PORTA4, PORTA3, PORTA2, PORTA1, PORTA0)
IAR_SFR_B_N(0x01, DDRA, DDA7, DDA6, DDA5, DDA4, DDA3, DDA2, DDA1, DDA0)
IAR_SFR_B_N(0x00, PINA, PINA7, PINA6, PINA5, PINA4, PINA3, PINA2, PINA1, PINA0)
#pragma language=restore
#endif /* __IOLGT8F0XA_H__ (SFR part) */
强人啊！{:smile:} uc_c++ 发表于 2012-4-16 16:41 static/image/common/back.gif
完整的头文件，不保证完全正确。
请问楼主,这个头文件在IAR中该怎样调用?因为如果我选上ATmega164A后会自动调用iom164a.h文件的,刚刚想试一下IAR,还不怎么会用这个平台.先谢了~~~ uc_c++ 发表于 2012-4-16 16:41
完整的头文件，不保证完全正确。
开头是__IOLGT8F0XA_H__
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