AD9854的初始相位怎么变化
要求：用AD9854输出4.6M的点频信号，周期性的，初始相位可控我的程序：
`timescale 1ns/1ns
module ad9854_text(
clk,
rst_n,
ad9854_clk,
ad9854_master,
ad9854_data,
ad9854_adress,
ad9854_wr,
ad9854_update
);
//输入信号
input clk;
input rst_n;
//输出信号
output ad9854_clk;
output ad9854_master;
output ad9854_update;
output ad9854_wr;
output ad9854_adress;
output ad9854_data;
localparam Width=10;
//复位信号
localparam master_begin=15;
localparam master_end=35;
localparam count_master_end=50;
//状态信号
localparam count_end=270;
//更新信号
localparam update_begin1=52;
localparam update_end1=53;
localparam update_begin2=160;
localparam update_end2=161;
//ad9854寄存器地址
localparam spec_addr=6'h1d;
localparam freq_addr1=6'h04;
localparam phase_addr1=6'h00;
//ad9854寄存器数据
localparam single_data={8'h40,8'h00,8'h46,8'h10};
localparam ad9854_fre={8'h03,8'hec,8'he2,8'ha5,8'h34,8'h91};
localparam ad9854_phase={8'h00,8'h00};
localparam ad9854_phase2={8'h00,8'h00};
reg count_state;
reg count_master;
reg ad9854_adress;
reg ad9854_data;
reg ad9854_wr;
reg ad9854_master;
reg ad9854_update;
reg flag_phase;
wire flag_master;
wire clk_r;
wire clk_out;
//同步输出
assign ad9854_clk=clk_out;
assign flag_master=(count_master==count_master_end);
IBUFG #(.IOSTANDARD("DEFAULT"))
IBUFG_inst
(
.O(clk_r),//Clockbufferoutput
.I(clk)//Clockbufferinput(connectdirectlytotop-levelport)
);
BUFG BUFG_inst(
.O(clk_out),//Clockbufferoutput
.I(clk_r)//Clockbufferinput
);
always @ (posedge ad9854_clk)
begin
if(!rst_n)
count_master<=0;
else if(count_master<count_master_end)
count_master<=count_master+1'b1;
else
count_master<=count_master_end;
end
always @ (posedge ad9854_clk )
begin
if(!rst_n)
count_state<=0;
else if(flag_master)
if(count_state<count_end)
count_state<=count_state+1'b1;
else
count_state<=0;
else
count_state<=0;
end
always @ (posedge ad9854_clk)
begin
if(!rst_n)
ad9854_master<=1'b0;
else if(count_master<=master_end&&count_master>=master_begin)
ad9854_master<=1'b1;
else
ad9854_master<=1'b0;
end
always@(posedge ad9854_clk)
begin
if(!rst_n)
flag_phase<=1'b0;
else if(count_state==0)
flag_phase<=~flag_phase;
end
always @(posedge ad9854_clk)
begin
if(!rst_n)
ad9854_wr<=1'b1;
else
case(count_state)
4,8,12,16,20,24,28,32,36,40,44,48,52,154,158,160:ad9854_wr<=1'b1;
2,5,9,13,17,21,25,29,33,37,41,45,49,152,155,159:ad9854_wr<=1'b0;
default:;
endcase
end
always @ (posedge ad9854_clk)
begin
if(!rst_n)
ad9854_update<=1'b0;
else if((count_state>=update_begin1&&count_state<=update_end1)||(count_state>=update_begin2&&count_state<=update_end2))
ad9854_update<=1'b1;
else
ad9854_update<=1'b0;
end
always @(posedge ad9854_clk)
begin
if(!rst_n)
begin
ad9854_adress<=6'h00;
ad9854_data<=8'h00;
end
else
case(count_state)
2:begin
ad9854_adress<=spec_addr;
ad9854_data<=single_data;
end
6:begin
ad9854_adress<=spec_addr+6'h01;
ad9854_data<=single_data;
end
10:begin
ad9854_adress<=spec_addr+6'h02;
ad9854_data<=single_data;
end
14:begin
ad9854_adress<=spec_addr+6'h03;
ad9854_data<=single_data;
end
18:begin
ad9854_adress<=phase_addr1;
// if(flag_phase)
ad9854_data<=ad9854_phase2;
// else
// ad9854_data<=ad9854_phase;
end
22:begin
ad9854_adress<=phase_addr1+6'h01;
// if(flag_phase)
ad9854_data<=ad9854_phase2;
// else
// ad9854_data<=ad9854_phase;
end
26:begin
ad9854_adress<=freq_addr1;
ad9854_data<=ad9854_fre;
end
30:begin
ad9854_adress<=freq_addr1+6'h01;
ad9854_data<=ad9854_fre;
end
34:begin
ad9854_adress<=freq_addr1+6'h02;
ad9854_data<=ad9854_fre;
end
38:begin
ad9854_adress<=freq_addr1+6'h03;
ad9854_data<=ad9854_fre;
end
42:begin
ad9854_adress<=freq_addr1+6'h04;
ad9854_data<=ad9854_fre;
end
46:begin
ad9854_adress<=freq_addr1+6'h05;
ad9854_data<=ad9854_fre;
end
152:begin
ad9854_adress<=6'h1f;
ad9854_data<=8'h40;
end
156:begin
ad9854_adress<=6'h20;
ad9854_data<=8'h20;
end
default:
begin
ad9854_adress<=ad9854_adress;
ad9854_data<=ad9854_data;
end
endcase
end
endmodule
我是延迟一段，两次的信号要反向，但是我只能做到满足0度~180度，其他度数不满足，所以我就不让它反向。
我让它初始相位为270度为：
我调试只能得到很好的0度和180度的反向：
其中的末尾的小毛刺可以通过调节update的位置可以去除。
求大家帮我看看，在下在此感激不尽 同求吧、、、、、
页:
[1]