求助：VHDL编译时出现ignored unnecessary INPUT pin警告
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;
ENTITY p_check IS
PORT(a:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
y:OUT STD_LOGIC);
END p_check;
ARCHITECTURE opt OF p_check IS
SIGNAL tmp:STD_LOGIC;
BEGIN
PROCESS(a)
BEGIN
tmp<='0';
FOR n IN 0 TO 3 LOOP
tmp<=tmp XOR a(n);
END LOOP;
y<=tmp;
END PROCESS;
END opt;
在maxplusII环境下操作，上面的程序在编译时出现ignored unnecessary INPUT pin警告。在仿真时，无法给a(0),a(1),a(2)加信号。请问如何解决啊。感激不尽。
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