关于FPGA与PIC16F877A实现PSP模式通信的问题。
各位好，本人打算用PIC的PSP模式从FPGA写入数据到单片机，但是FPGA写入的数据总是错误，不知道为什么？
控制代码如下：
--FPGA主动并行端口控制模块：Host_control.vhd
Library IEEE;
Use IEEE.std_logic_1164.ALL;
Entity Host_control Is
Generic (n : Integer := 100);
Port(clock : In Std_logic; --时钟信号
reset : In Std_logic; --复位信号，低电平有效
writeEN : In Std_logic; --写PIC使能
inData : In Std_logic_vector(7 DownTo 0); --输入数据
CS : Out Std_logic; --PIC片选信号，低电平有效
WR : Out Std_logic; --PIC写使能信号，低电平有效
RD : Out Std_logic; --PIC读使能信号，低电平有效
outData : Out Std_logic_vector(7 DownTo 0) --输出到PIC的数据
--ADC_FIFO读控制
-- rdreg : Out Std_logic; --ADC_FIFO读使能，高电平有效
-- rclock : Out Std_logic --ADC_FIFO读时钟
);
End Entity Host_control;
Architecture rtl Of Host_control Is
--Signal
Type states Is (rst,write,WriteEnd,await0,await1); --定义3种工作状态，复位、写数据和等待
Signal current_state,next_state : states := rst;
Signal count : Integer Range 0 To n := 0; --计数信号
Signal WR1 : Std_logic; --PIC写使能信号，低电平有效
Begin
WR <= WR1;
Process(clock,reset,next_state)
Begin
If(reset = '0') Then
current_state <= rst;
ElsIf(Rising_edge(clock)) Then
current_state <= next_state;
End If;
End Process;
Process(current_state,writeEN)
Begin
Case current_state Is
When rst => CS <= '1'; WR1 <= '1'; RD <= '1'; --复位
outData <= x"f0";
next_state <= await0;
When write => CS <= '0'; WR1 <= '0'; RD <= '1'; --写数据到PIC
outData <= x"f0";
next_state <= await1;
When await1 => CS <= '0'; WR1 <= '0'; RD <= '1'; --写数据到PIC
outData <= x"f0";
next_state <= WriteEnd;
When WriteEnd => CS <= '0'; WR1 <= '1'; RD <= '1'; --写数据结束
outData <= x"f0";
If(writeEN = '0') Then --等待IBF输入缓冲标志置一
next_state <= writeEnd;
Else
next_state <= await0;
End If;
-- When await1 => CS <= '1'; WR1 <= '1'; RD <= '1'; --等待1个周期
-- next_state <= await0;
-- When await1 => CS <= '1'; WR1 <= '1'; RD <= '1'; --等待1个周期
-- next_state <= await2;
When await0 => CS <= '1'; WR1 <= '1'; RD <= '1'; --等待1个周期
outData <= x"f0";
If(writeEN = '0') Then --判断是否可使能
next_state <= write;
Else
next_state <= await0;
End If;
When Others => CS <= '1'; WR1 <= '1'; RD <= '1';
outData <= x"f0";
next_state <= rst;
End Case;
End Process;
-- Process(clock,WR1) --锁存输出数据
-- Begin
-- If(Rising_edge(clock)) Then
-- If(WR1 = '1') Then
-- outData <= x"f0";
-- End If;
-- End If;
-- End Process;
-- rclock <= clock; --读ADC_FIFO时钟
-- Process(clock,next_state) --读ADC_FIFO使能控制
-- Begin
-- If(Rising_edge(clock)) Then
-- If(next_state = write) Then
-- rdreg <= '1'; --读使能
-- Else
-- rdreg <= '0';
-- End If;
-- End If;
-- End Process;
-- cnt : Process(clock,reset,writeEN) --计数器
-- Begin
-- If(reset = '0') Then
-- count <= 0;
-- ElsIf(Rising_edge(clock)) Then
-- If(writeEN = '1') Then
-- count <= count+1;
-- Else
-- count <= 0;
-- End If;
-- End If;
-- End Process cnt;
End Architecture rtl;
时钟是一个50MHz时钟经过100分频得到的。
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