用VHDL编个VGA的程序，怎么屏幕没反应？？？
------------------------------------------------------------------------------------ Company:
-- Engineer:
--
-- Create Date: 13:59:55 12/27/2011
-- Design Name:
-- Module Name: VGA - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity VGA is
port(
reset :in std_logic;
clk :in std_logic;
vga_hs:out std_logic;
vga_vs:out std_logic;
vga_red:out std_logic;
vga_green:out std_logic;
vga_blue:out std_logic
);
end VGA;
architecture Behavioral of VGA is
signal hs:std_logic;
signal vs:std_logic;
signal RGB:std_logic_vector(2 downto 0);
begin
PROCESS(clk)
VARIABLE i: integer range 0 to 799:=0;
VARIABLE j: integer range 0 to 79:=0;
BEGIN
if reset='0' then
RGB<="000";i:=96;j:=0;hs<='1';
elsif clk'event and clk='1' then
if i<96 then
hs<='0';
elsif i=799 then
i:=0;
else
hs<='1';
end if;
if j=79 then
RGB(1)<=not RGB(1);
j:=0;
end if;
i:=i+1;
j:=j+1;
end if;
vga_hs<=hs;
end process;
PROCESS(hs)
VARIABLE k: integer range 0 to 524:=0;
BEGIN
if reset ='0' then
k:=2;vs<='1';
elsif hs'event and hs='1' then
if k<2 then
vs<='0';
elsif k=524 then
k:=0;
else
vs<='1';
end if;
k:=k+1;
end if;
Vga_vs<=vs;
end process;
process(clk)
begin
if clk'event and clk='1' and vs='1' and hs='1' then
vga_green<=RGB(2);
vga_red<=RGB(1);
vga_blue<=RGB(0);
end if;
end process;
end Behavioral; 请高手看看怎么回事 楼主,用ISE 编某个引脚输出低电平,该怎么写(新手不懂)
我看ISE资料上说,用Assign Pin Location 配置引脚,失败不行,还望解答 不显示，检查下引脚，如果引脚没错的话，就应该是时序问题 至少先用示波器看下输出吧，原来你在南京呀，有硬件？ LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; 时钟50M,800*600 72Hz疯子王
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY VGA IS
PORT(
CLK:IN STD_LOGIC;
HS:OUT STD_LOGIC;
VS:OUT STD_LOGIC;
R:OUT STD_LOGIC_VECTOR(2 downto 0);
G:OUT STD_LOGIC_VECTOR(2 downto 0);
B:OUT STD_LOGIC_VECTOR(1 downto 0)
);
END ENTITY;
ARCHITECTURE ART OF VGA IS
SIGNAL hcnt,vcnt:STD_LOGIC_VECTOR(10 DOWNTO 0);
BEGIN
PROCESS(CLK)
BEGIN
IF(CLK'EVENT AND CLK='1')THEN
IF(hcnt=1039) THEN
hcnt<=(others=>'0');
IF(vcnt=665) THEN
vcnt<=(others=>'0');
ELSE
vcnt<=vcnt+1;
END IF;
ELSE
hcnt<=hcnt+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLK)
BEGIN
IF(CLK'EVENT AND CLK='1')THEN
IF(hcnt>=119) THEN
HS<='1';
ELSE
HS<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLK)
BEGIN
IF(CLK'EVENT AND CLK='1')THEN
IF(vcnt>=5) THEN
VS<='1';
ELSE
VS<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLK)
BEGIN
IF(CLK'EVENT AND CLK='1')THEN
IF((hcnt>=175 AND hcnt<=975) AND (vcnt>=42 AND vcnt<=642) ) THEN
R<="111";
G<="000";
B<="00";
ELSE
R<="000";
G<="000";
B<="00";
END IF;
END IF;
END PROCESS;
END ART; zgq800712 发表于 2011-12-30 23:53
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; 时钟50M,800*600 72Hz疯子王
USE IEEE.STD_ ...
这个程序用的是ADV7123芯片吗？
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