ram_is61lv256的verilog代码，
//大学时候写的代码，希望对大家有所帮助/*/////////////////////////////////////////////////////////////
ram_is61lv256的verilog代码，
/////////////////////////////////////////////////////////////*/
module ram_is61lv256
(
clk, //5Mhz clock in
sys_clk, //50Mhz clock in
delay_time, //delay timecontrol
w_dat, //12_bit data in from ad to ram
ram_dat_16, //ram's io
addr, //ram's address
ce, //chip enable
we, //read (H) and write (L)
oe, //output enable
r_dat, //12_bit data from ram out to da
ram_rst, //rest
ram_start, //ram 转换控制端
en_read,
UB,
LB
);
input clk,ram_rst,ram_start,sys_clk;
input wire delay_time; //delay timecontrol
input wire w_dat;
regw_dat_t;
output reg r_dat;
inout ram_dat_16;
output reg ce,oe,we,UB,LB;
output reg addr;//ram address
//reg addr_w; //write address
//reg addr_r; //readaddress
output reg en_read; //en_read=1 ->enable read
reg flag; //flag=1->write ram
reg wdat_cnt; //count write_addr
reg rdat_cnt; //count read_addr
reg state;
parameter Idle =8'b00000001;
parameter WRITE =8'b00000010;
parameter WRITE_1 =8'b00000100;
parameter WRITE_end =8'b00001000;
parameter WR_to_RD =8'b00010000;
parameter READ_0 =8'b00100000;
parameter READ =8'b01000000;
parameter READ_end =8'b10000000;
assign ram_dat_16=flag?{4'b000,w_dat_t}:16'hzzzz; //flag=1 -> write data
////////////////////////////////////////////////////////////////////////////////
reg ram_start_reg;
always @ ( posedge clk or negedge ram_rst )
if(!ram_rst)
ram_start_reg <= 3'b000;
else
ram_start_reg <= {ram_start_reg,ram_start};
wire ram_start_en;
assign ram_start_en = ( ram_start_reg == 2'b01 ) ;
///////////////////////////////////////////////////////////////////////////////
reg state_delay;
reg delay_time_bfore;
reg delay_time_after;
reg en_clr;
regcnt;
parameter before =2'b01;
parameter after =2'b10;
always @(posedge sys_clk or negedge ram_rst)
if(!ram_rst)
begin
state_delay<=before;
en_clr<=0;
cnt<=0;
delay_time_bfore<=0;
delay_time_after<=0;
end
else begin
case(state_delay)
before: begin delay_time_bfore<=delay_time; state_delay<=after; end
after:begin delay_time_after<=delay_time; state_delay<=before;end
default;
endcase
if((delay_time_bfore-delay_time_after)!=0)
beginen_clr<=1; cnt<=0; end
//if(en_clr==1) cnt<=0;
cnt<=cnt+1;
if(cnt==3125)en_clr<=0;
end
always @(posedge clk or negedge ram_rst)
if(!ram_rst)
begin
ce<=1;
wdat_cnt<=0;
rdat_cnt<=0;
en_read<=0;
flag<=0;
state<=Idle;
ce<=1;
oe<=1;
we<=1;
UB<=0;
LB<=0;
w_dat_t<=0;
end
else begin
case(state)
Idle:
begin
if(ram_start_en==1)
begin
state<=WRITE;
flag<=0;
we<=1;
ce<=1;
oe<=1;
//UB<=0;
//LB<=0;
addr<=wdat_cnt;
end
else
begin
state<=Idle;
oe<=1;
ce<=1;
we<=1;
if(en_clr)
begin
wdat_cnt<=0;
rdat_cnt<=0;
en_read<=0;
end
end
end
WRITE:
begin
we<=0;
ce<=0;
if(wdat_cnt>=delay_time)beginwdat_cnt<=0;end
else wdat_cnt<=wdat_cnt+1;
state<=WRITE_1;
end
WRITE_1:
begin
flag<=1;
w_dat_t<=w_dat;
state<=WRITE_end;
end
WRITE_end:
begin
we<=1;
ce<=1;
flag<=0;
state<=WR_to_RD;
end
WR_to_RD:
begin
w_dat_t<=0;
if(wdat_cnt>=delay_time-1)begin en_read<=1;end
if(en_read)
begin
if(rdat_cnt>=delay_time)beginrdat_cnt<=0;end
else rdat_cnt<=rdat_cnt+1;
end
else begin r_dat<=0; rdat_cnt<=0; end
state<=READ_0;
end
READ_0:
begin
addr<=rdat_cnt;
state<=READ;
end
READ:
begin
if(en_read)
begin
ce<=0;
oe<=0;
end
else r_dat<=0;
state<=READ_end;
end
READ_end:
begin
if(en_read) r_dat<=ram_dat_16;
state<=Idle;
end
default state<=Idle;
endcase
end
endmodule mark.正在把SRAM写成一个FIFO，控制起来方便点 Chouc 发表于 2012-4-24 00:26 static/image/common/back.gif
mark.正在把SRAM写成一个FIFO，控制起来方便点
现在完成得怎样，SRAM变FIFO有开源不？ mark mark
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