美信ad芯片max1301的verilog代码
//大学时候写的，虽然很简单但是还是拿出来晒一下/*/////////////////////////////////////////////////////////////
美信ad芯片max1301的verilog代码
/////////////////////////////////////////////////////////////*/
module max1301(
sys_clk, //系统时钟50M
ad_out, //接ad的输出端 Dout
ad_rest, //ad的复位端
ad_start, //ad转换控制端
/*输出端*/
ad_bus, //数据总线
ad_in, //接ad的输入端 Din
ad_cs, //接ad片选端 cs
ad_clk, //接ad时钟端 sclk
data_receive_done,//接下一个模块的片选
bit_counter_s,
ad_start_en
);
input sys_clk,ad_start,ad_out,ad_rest;//clk莂d控制器的时钟,也是ad的时钟.
output reg ad_bus;//数据总线
outputad_in,ad_clk;
output reg ad_cs;
output reg data_receive_done;
reg state,next_state;
parameter idle =7'b0000001;
parameter load_Config_B=7'b0000010;
parameter send_Config_B=7'b0000100;
parameter load_Mode_B =7'b0001000;
parameter send_Mode_B =7'b0010000;
parameter load_receive_B =7'b0100000;
parameter receive =7'b1000000;
reg data_shfreg_1;
reg data_shfreg_2;
reg data_receive;
reg ad_data;
/////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////
reg ad_start_reg;
always @ ( posedge sys_clk or negedge ad_rest )
if(!ad_rest)
ad_start_reg <= 3'b000;
else
ad_start_reg <= {ad_start_reg,ad_start};
output wire ad_start_en;
assign ad_start_en = ( ad_start_reg == 2'b01 ) ;
reg load_Config;
reg shift_Config;
reg load_Mode;
reg shift_Mode;
reg load_receive;
reg shift_receive;
reg ad_clk_en;
reg load_bus;
reg bit_counter_1;
reg bit_counter_2;
output reg bit_counter_s;
always@(state or bit_counter_1 or bit_counter_2 or ad_start_en or bit_counter_s)
begin
load_Config=0;
shift_Config=0;
load_Mode=0;
shift_Mode=0;
load_receive=0;
shift_receive=0;
load_bus=0;
next_state=state;
case(state)
idle:
if(ad_start_en==1)
begin
next_state=load_Config_B;
ad_clk_en=0;
ad_cs=1;
data_receive_done=0;
// data_receive=0;
end
else
begin
next_state=idle;
ad_clk_en=0;
ad_cs=1;
data_receive_done=0;
end
load_Config_B:
begin
load_Config=1;
ad_cs=0;
next_state=send_Config_B;
end
send_Config_B:
if(bit_counter_1<=7)
begin
ad_clk_en=1;
shift_Config=1;
end
else
begin
next_state=load_Mode_B;
ad_cs=1;
ad_clk_en=0;
end
load_Mode_B:
begin
load_Mode=1;
ad_cs=0;
next_state=send_Mode_B;
end
send_Mode_B:
if(bit_counter_2<=7)
begin
ad_clk_en=1;
shift_Mode=1;
end
else
begin
ad_cs=1;
ad_clk_en=0;
next_state=load_receive_B;
end
load_receive_B:
begin
load_receive=1;
ad_cs=0;
next_state=receive;
end
receive:
if(bit_counter_s<=15)
begin
//data_receive=16'hff00;//{data_receive,1'b1};
ad_cs=0;
ad_clk_en=1;
shift_receive=1;
end
else if(bit_counter_s<=30)
begin
ad_cs=0;
ad_bus=data_receive;
ad_clk_en=1;
shift_receive=1;
end
else if(bit_counter_s==31)
begin
ad_clk_en=0;
shift_receive=1;
end
else
begin
next_state=idle;
load_bus=1;
data_receive_done=1;
// ad_bus=data_receive;
ad_cs=1;
ad_clk_en=0;
end
default next_state=idle;
endcase
end
always @(posedge sys_clk or negedge ad_rest)
if(!ad_rest)state<=idle;else state <=next_state;
always @(negedge sys_clk or negedge ad_rest)
begin
if(!ad_rest)begin
data_shfreg_1<=8'hff;
data_shfreg_2<=8'hff;
bit_counter_1<=0;
bit_counter_2<=0;
end
else
begin
case({load_Config , shift_Config , load_Mode , shift_Mode})
4'b1000:
begin data_shfreg_1<={8'h84}; bit_counter_1<=0; end
4'b0100 :
begin
data_shfreg_1<={data_shfreg_1,1'b0};
bit_counter_1<=bit_counter_1+1;
end
4'b0010 :
begin data_shfreg_2<={8'h88}; bit_counter_2<=0; end
4'b0001 :
begin
data_shfreg_2<={data_shfreg_2,1'b0};
bit_counter_2<=bit_counter_2+1;
end
default;
endcase
end
end
always @(posedge sys_clk or negedge ad_rest)
begin
if(!ad_rest)begin
bit_counter_s<=0;
data_receive<=0;
end
else
begin
if(bit_counter_s>33)data_receive<=0;
else data_receive<={data_receive,ad_out};
case({load_receive , shift_receive} )
2'b10:
beginbit_counter_s<=0; end
2'b01:
begin
bit_counter_s<=bit_counter_s+1;
end
default;
endcase
end
end
assign ad_in=(load_receive)? 1'b1 : ((state==load_Config_B||state==send_Config_B)?data_shfreg_1:data_shfreg_2);
//assign ad_bus=ad_data;
assign ad_clk=ad_clk_en?sys_clk:0;
endmodule
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