课程设计之【基于FPGA的串口通信模块设计】
最近一共代同学做了五个课程设计，这是其中之一。放在电脑里太浪费，所以发上论坛和大家一起分享、交流和学习。待其他课设验收完，后续将会陆续上传。这个文件主要包括三个模块：发送，接收，按键防抖。实现RS232串口的接收和发送功能。可自己在参数里设置波特率。其中按键防抖用的是网上现成的模块，不知是谁的,其他的为原创。时钟50Mhz，HDL用的是Verilog。
点击此处下载 ourdev_700460R6DMCH.rar(文件大小:1.75M) (原文件名:RS232.rar)
http://cache.amobbs.com/bbs_upload782111/files_48/ourdev_700459IODKBZ.jpg
(原文件名:串口模拟.jpg) //////////////////Transmit.v////////////////////////////
module Transmit(
clk, //System Clock 50Mhz
data_in, //8-bits pararel data input
tx_en, //Transmit enable:posedge is effective
tx, //Serial output port
busy, //Busy flag. High is effective
);
input clk;
input data_in;
input tx_en;
output busy;
output tx;
reg busy=0;
reg tx=1;
reg tx_reg=0;
reg clk_d=0;
reg state=0;
reg en_pos=0;
wire tx_cs;
/*************Generate Baud rate************/
parameter BAUD_RATE=9600;//Clock=50Mhz,BD=9600bps
integer count=0;
always @(posedge clk)
begin
count <=count+1;
if(count==(25000000/BAUD_RATE))
begin
clk_d <=~clk_d;
count <=0;
end
end
/***********Generate Control Timing************/
assign tx_cs=en_pos&~tx_en;
always @(posedge clk_d)
begin
en_pos <=tx_en;
end
/**************Send Serial Data***************/
parameter
IDLE =10'b0000000001,
START=10'b0000000010,
BIT_0=10'b0000000100,
BIT_1=10'b0000001000,
BIT_2=10'b0000010000,
BIT_3=10'b0000100000,
BIT_4=10'b0001000000,
BIT_5=10'b0010000000,
BIT_6=10'b0100000000,
BIT_7=10'b1000000000;
always @(posedge clk_d or posedge tx_cs)
begin
if(tx_cs)
begin
state <=START;
tx_reg <=data_in;
busy <=1;
end
else
begin
case(state)
IDLE: begin tx<=1; busy<=0; state<=IDLE ; end
START:begin tx<=0; state<=BIT_0; end
BIT_0:begin tx<=tx_reg;state<=BIT_1; end
BIT_1:begin tx<=tx_reg;state<=BIT_2; end
BIT_2:begin tx<=tx_reg;state<=BIT_3; end
BIT_3:begin tx<=tx_reg;state<=BIT_4; end
BIT_4:begin tx<=tx_reg;state<=BIT_5; end
BIT_5:begin tx<=tx_reg;state<=BIT_6; end
BIT_6:begin tx<=tx_reg;state<=BIT_7; end
BIT_7:begin tx<=tx_reg;state<=IDLE ; end
endcase
end
end
endmodule /***************************Receive.v***************************/
module Receive(
clk, //50MHZ
rx, //Serial data input
data_out,//Pararel data output
busy, //Busy flag. High level is effective.
);
input clk;
input rx;
output data_out;
output busy;
reg data_out=0;
reg busy=0;
reg clk_bd=0;
reg state=0;
reg rx_reg=0;
/*************Generate Baud rate************/
parameter BAUD_RATE=9600;//Clock=50Mhz,BD=9600bps
integer count=0;
always @(posedge clk)
begin
count <=count+1;
if(count==(25000000/BAUD_RATE))
begin
clk_bd <=~clk_bd;
count <=0;
end
end
/**************Recieve Serial Data***************/
parameter
IDLE =10'b0000000001,
BIT_0=10'b0000000100,
BIT_1=10'b0000001000,
BIT_2=10'b0000010000,
BIT_3=10'b0000100000,
BIT_4=10'b0001000000,
BIT_5=10'b0010000000,
BIT_6=10'b0100000000,
BIT_7=10'b1000000000;
always @(posedge clk_bd)
begin
if(!rx && !busy)
begin
state <=BIT_0;
busy<=1;
end
else
begin
case(state)
IDLE: begin
data_out<=rx_reg;
state<=IDLE ;
busy<=0;
end
BIT_0:begin rx_reg<=rx;state<=BIT_1; end
BIT_1:begin rx_reg<=rx;state<=BIT_2; end
BIT_2:begin rx_reg<=rx;state<=BIT_3; end
BIT_3:begin rx_reg<=rx;state<=BIT_4; end
BIT_4:begin rx_reg<=rx;state<=BIT_5; end
BIT_5:begin rx_reg<=rx;state<=BIT_6; end
BIT_6:begin rx_reg<=rx;state<=BIT_7; end
BIT_7:begin rx_reg<=rx;state<=IDLE ; end
endcase
end
end
endmodule 采样一次？ 不错如果有源码就更好了 学习一下
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