cyclone ii 器件连接DDR 内存 笔记。
打算在FPGA 内采用DDR内存以前从来没用过
现在开始记录自己的学习经历吧：
资料在这：
http://www.altera.com.cn/literature/hb/cyc2/cyc2_cii51009.pdf
上面写了：
You can use any of the user I/O pins for commands and addresses.
Because of the symmetrical setup and hold time for the command and
address pins at the memory device, you may need to generate these
signals from the negative edge of the system clock.
地址线可以用任意的IO。
The clocks to the SDRAM device are called CK and CK#. Use any of the
user I/O pins via the DDR registers to generate the CK and CK# signals
to meet the tDQSS requirements of the DDR SDRAM or DDR2 SDRAM
device. The memory device’s tDQSS requires the positive edge of the write
DQS signal to be within 25% of the positive edge of the DDR SDRAM and
DDR2 SDRAM clock input. Because of strict skew requirements between
CK and CK# signals, use adjacent pins to generate the clock pair.
Surround the pair with buffer pins tied to VCC and pins tied to ground for
better noise immunity from other signals.
时钟 必须从DDR 寄存器？ 这是什么意思呢？ altera 说 CK CK# 用普通的IO 就行，这样行么？
对了 还看到 说CK CK# 还有DQS DQ啥的不能在一个bank？
忘了在哪看到的。。
who 搞过啊？ 手册上这么说：
CK/CK# pins must be placed on differential I/O pins and cannot be placed on the
same row or column as the DQ pins. 关于DDR的时钟
有这么一篇帖子：
http://www.alteraforum.com/forum/showthread.php?t=21549
我也很疑惑这个问题 手上有旧的笔记本内存一直想用起来，学习一下。 关于DDR的时钟
看到一块板子上 是用的pll 以及pll# 来做的 但是资料写是用任意IO都行 mark mark 今天试了下 加了一个DDR IP 然后分配管脚了。。
有这么一个信号，不知道是啥用处
还有DDR 控制器好像没用到PLL
write_clk_to_the_ddr_sdram
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