一个CPLD PWM产生器，在比较器中duty参数传递不成功，请高手指导
verilog源程序如下.在比较器模块，duty参数传递好像不成功，因为无论输入信号CUR如何变化，PREF脚的输出占空比始终是50%，而如果将pwmref <= (counter2>duty1)? 0 : 1;中的duty1变成常量比如10，则输出占空比是10%
module motor_ctrl (
input RST_INput , //actived High
output PREF ,
input CUR ,
input clk0_in
);
reg pwmref ;
reg duty ;
reg duty1 ;
reg cur_value ;
reg counter1 ;
reg counter2;
assign RST_IN = ~RST_INput;
assign PREF = pwmref;
//////////////////////////////////////////////////////计数器,用于产生PWM
always @ (posedge RST_IN or posedge clk0_in) begin
if (RST_IN==1'b1) begin
counter1 <= 7'h00;
end
else begin
counter1 <= counter1 + 1;
end
end
////////////////////////////////////////////////////////////读拨码开关,电流值
always @ (posedge RST_IN or posedge clk0_in) begin
if (RST_IN==1'b1) begin
cur_value <= 3'b000;
duty <= 0;
end
else begin
cur_value <= CUR;
duty1 <= duty;
case (cur_value)
3'b000: duty <= 7'h7f;//127
3'b001:duty <= 7'h75;//117;
3'b010:duty <= 7'h6a;//106;
3'b011: duty <= 7'h5f;//95;
3'b100:duty <= 7'h55;//85;
3'b101:duty <= 7'h4a;//74;
3'b110:duty <= 7'h40;//64;
3'b111:duty <= 7'h35;//53;
default:duty <= 7'h00;
endcase
end
end
///////////////////////////////////////////////////////////比较器,PWM产生
always @ (posedge RST_IN or posedge clk0_in) begin
if (RST_IN==1'b1) begin
pwmref <= 1'b0;
end
else begin
duty1 <= duty;
counter2 <= counter1;
pwmref <= (counter2>duty1)? 0 : 1;
end
end
endmodule 没一个人回帖，我自己顶
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