一步一步学CPLD+SRAM驱动tft4.3寸液晶屏(连载。。。。)
学习cpld也有相当一段时间了,一直没有实战应用,借着要给单位做个测试板的机会,玩玩cpld驱动TFT.现在市面上的tft4.3寸液晶屏满天飞,价格很便宜可能是MP5畅销的缘故吧
硬件支持背光,触摸屏, flashAT45db161d, sd卡。
不费话了先上原理图
tft43原理图ourdev_685080WXAWB7.pdf(文件大小:498K) (原文件名:TFT43_DRI.pdf)
电路板昨天收到了已焊接成品
http://cache.amobbs.com/bbs_upload782111/files_46/ourdev_685088C047ZM.jpg
(原文件名:IMAG0028.jpg)
http://cache.amobbs.com/bbs_upload782111/files_46/ourdev_685089QURQZJ.jpg
(原文件名:IMAG0029.jpg)
http://cache.amobbs.com/bbs_upload782111/files_46/ourdev_685090IS7LBI.jpg
(原文件名:IMAG0031.jpg)
http://cache.amobbs.com/bbs_upload782111/files_46/ourdev_685091XNZIJF.jpg
(原文件名:IMAG0032.jpg) 通用的4.3寸TFT时序图
http://cache.amobbs.com/bbs_upload782111/files_46/ourdev_685094QXBEGB.jpg
(原文件名:时序.jpg)
逻辑代码正在编写中。。。。。。。待续 果断的插入 mark,速度 续 时钟分配
采用widesoft1 大侠的http://www.ourdev.cn/bbs/bbs_content.jsp?bbs_sn=4534978&bbs_page_no=1&search_mode=1&search_text=tft&bbs_id=1029
vhdl编写
STAUSCNT最高位STAUSCNT(2)是送往TFT43的9M时钟
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity pll4f is
port (
signal CLK : IN STD_LOGIC;
signal STAUSCNT : BUFFER STD_LOGIC_VECTOR (2 DOWNTO 0)
);
end entity pll4f;
architecture pll4 of pll4f is
begin
process (CLK)
begin
IFCLK' EVENT AND CLK='1' THEN
IF STAUSCNT="110" THEN
STAUSCNT<="001";
ELSE
STAUSCNT<=STAUSCNT+1;
END IF;
END IF;
end process;
end pll4;
TFT43时序
DCK连接时钟STAUSCNT(2)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity TFT43OUT is
port (
signal DCK : IN STD_LOGIC;
signal InData : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal R_Data : out STD_LOGIC_VECTOR (4 DOWNTO 0);
signal G_Data : out STD_LOGIC_VECTOR (5 DOWNTO 0);
signal B_Data : out STD_LOGIC_VECTOR (4 DOWNTO 0);
--signal Adr : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
signal DEN : buffer STD_LOGIC;
signal Adr : out STD_LOGIC_VECTOR (16 DOWNTO 0);
signal HS,VS,DCK1 : out STD_LOGIC;
signal LEDP : buffer STD_LOGIC_VECTOR (5 DOWNTO 0)
);
end entity TFT43OUT;
architecture TFTOUT of TFT43OUT is
signal ADr_out:STD_LOGIC_VECTOR (16 DOWNTO 0);
begin
---------------------------------------------------------------------------
Adr<=ADr_out;
DCK1<=DCK;
---------------------------------------------------------------------------
process (DCK,ADr_out)
variable Hreg_Q : STD_LOGIC_VECTOR (9 DOWNTO 0);
variable Vreg_Q : STD_LOGIC_VECTOR (8 DOWNTO 0);
begin
IFDCK' EVENT AND DCK='1' THEN
IF(Hreg_Q<"1000010100") then -----------531
Hreg_Q:=Hreg_Q+1;
ELSE Hreg_Q:="0000000000";
LEDP<=LEDP+1;
IF Vreg_Q<"100011111"THEN --287
Vreg_Q:=Vreg_Q+1;
ELSE Vreg_Q:="000000000";
END IF;
END IF;
IFHreg_Q<"11" THEN --2
HS<='0';
else
HS<='1';
END IF;
IFVreg_Q <"100" THEN ---2
VS<='0';
ELSE VS<='1';
END IF;
IF Vreg_Q>"1100" AND Vreg_Q<"100011101"THEN --V13--284
IF Hreg_Q>"101010" ANDHreg_Q<"1000001011" THEN --H43-522
DEN<='1';
ADr_out<=ADr_out+1;
ELSE DEN<='0';
END IF;
ELSEADr_out<="00000000000000000";
END IF;
END IF;
end process;
process (DEN,InData)
begin
if DEN='1' then --可改变不同的颜色
R_Data<="00000";
G_Data<="000000";
B_Data<="11111";
else
R_Data<="00000";
G_Data<="000000";
B_Data<="00000";
end if;
end process;
end TFTOUT;
经过上面的代码可显示
http://cache.amobbs.com/bbs_upload782111/files_46/ourdev_685106OAQ0S1.jpg
(原文件名:IMAG0037.jpg)
http://cache.amobbs.com/bbs_upload782111/files_46/ourdev_685107YWAAHB.jpg
(原文件名:IMAG0038.jpg) 我想问下,MAX II, 就那么大点资源,驱动完TFT后还能做什么?我最近也在学习,但总感觉EMP240资源好少,写个动态驱动数码管的就占了1/3的资源,郁闷~ 回复【5楼】yuyu87 雨
我想问下,max ii, 就那么大点资源,驱动完tft后还能做什么?我最近也在学习,但总感觉emp240资源好少,写个动态驱动数码管的就占了1/3的资源,郁闷~
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基本就完了,就连io都完了 SD卡和FLASH做什么的呀?只是IO引出来? 不错。。mark mark一下 mark 问一下用FPGA中的程序在断电后会消失吗 是sof格式的 初学者多多指教哈 强力围观中......... 这一块的成本多少呀?楼主核算下没,能到150以内吗? hao 回复【12楼】niba
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用我的屏和触摸屏的话,可以控制到很低成本 核算下
屏 -------70
EPM240 ---15
SRAM -----15
PCB-----15
其他IC ---30
杂项 -----5
总硬件成本150 ,大家也合算下看看 呵呵,楼上很会算哦,不过我初学者玩意,昨天调试未完成,8088总线写入雪花点,进一步试验中 最好整下SDRAM啊 11.17还是那样没进展,进一步试验 正在学习这个,不错 楼主也是西安的? mark 回复【21楼】xibu1102007
楼主也是西安的?
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近年,单位大搬家,咸阳 mark EPM240资源够不够?。。。。。。够呛吧。。 这个以前坛子里面有人弄过的吧,可以找找看。 用了本论坛网友通关的代码显示出来了,呵呵做了个简单的界面
http://cache.amobbs.com/bbs_upload782111/files_47/ourdev_689128SOA253.jpg
(原文件名:IMAG0039.jpg)
http://cache.amobbs.com/bbs_upload782111/files_47/ourdev_689129P7MZB7.jpg
(原文件名:IMAG0040.jpg)
http://cache.amobbs.com/bbs_upload782111/files_47/ourdev_689130GR7Z4U.jpg
(原文件名:IMAG0041.jpg)
相关视频
点击此处下载 ourdev_689131EQ49YV.rar(文件大小:1.69M) (原文件名:VIDEO0003.rar) 这是全部代码,DE驱动,HSync 固定低电平
感谢widesoft2 通关的代码原帖
http://www.ourdev.cn/bbs/bbs_content.jsp?bbs_sn=4799753&bbs_page_no=1&search_mode=3&search_text=widesoft2&bbs_id=1029
/*
接口说明:
Clk54:系统晶振,选择54M晶振
SysRst:系统复位线.
ExDataBus:外部16位数据总线
ExCs:控制器片选,
ExRs:数据批令选择
ExWr:写信号
ExRd:读信号
RamAddrBus:显存地址线.
RamDataBus:显存数据总线
RamCs:显存片选
RamWe:显存写选通.
LedOn:背光控制PWM
DE:TFT屏
DE:VSyncTFT屏,
HSync:TFT屏
RGB:TFT屏
Pclk:TFT屏);
*/
module Tft_dri43(Clk54, SysRst, ExDataBus, ExCs, ExRs, ExWr, ExRd, RamAddrBus,
RamDataBus, RamCs, RamWe, LedOn, DE, VSync, HSync, RGB, Pclk, RamOe);
input Clk54, SysRst, ExCs, ExRs, ExRd, ExWr;
inout ExDataBus;
inout RamDataBus;
output RamAddrBus;
output RGB;
output RamCs, RamWe, LedOn, DE, VSync, HSync, Pclk,RamOe;
reg ClkCnt_Q3;
reg DotClkEn_Q;
reg Pclk_Q;
reg WrEn_Q;
reg ExBusOut_Q;
reg ExOutM;
reg WriteRgb_Q;
reg ExWrClk_Q;
reg ExRsR_Q;
reg ExCsR_Q;
reg ExRdClk_Q;
reg ExRdClk_Q1;
reg ExRdClk_Q2;
reg ExRdClk_Q3;
reg ExWrClk_Q1;
reg ExWrClk_Q2;
reg ExWrClk_Q3;
reg SramAddr;
reg PrePareData;
reg IndexData;
reg InRamWe;
reg IncAddr;
reg XRegOver;
reg YRegOver;
reg AskWr;
reg RGB_Q;
reg InBusOut_Q;
reg XRegValue_Q;
reg YRegValue_Q;
reg SysCmdValue_Q;
reg RegAddr_Q;
reg RamWeReg_Q;
reg RamTriState_Q;
reg FillCount_Q;
reg BRGBValue_Q;
reg FRGBValue_Q;
reg RamAddrBus_Q;
reg FillHead_Q;
reg HsCount_Q;
reg DotCount_Q;
reg SelDispRam_Q;
reg RamCsReg_Q;
reg DsMark;
reg HsMark;
reg DsState_Q;
reg HsState_Q;
reg DE_Q;
reg LedCount_Q;
reg LedOn_Q,LedOn_W;
assign Pclk = Pclk_Q;
assign RGB = RGB_Q;
assign RamAddrBus = RamAddrBus_Q;
assign RamWe = RamWeReg_Q;
assign RamCs = RamCsReg_Q;
assign RamDataBus = (RamTriState_Q | Clk54)?16'bzzzzzzzzzzzzzzzz:InBusOut_Q;
assign VSync = DE_Q;
assign HSync = 1'b0;
assign DE = DE_Q;
assign LedOn = LedOn_Q;//1'b1;
assign ExDataBus = ExOutM;
assign RamOe=1'b0;
/*
--1.将54M主时钟6分频,产生9M时钟并输出至引脚Pclk
--2.输出DotClkEn为9M信号同步其他进程.高电平为1个主时钟周期,低电平5个主时钟周期
--3.技巧: 001,010,011,100,101,110.共6个状态,高位刚好是6分频等宽.
*/
always @(posedge Clk54 or negedge SysRst)
begin
if (!SysRst) begin
ClkCnt_Q3 = 3'd1;
Pclk_Q = 1'b0;
DotClkEn_Q= 1'b0;
end else begin
if (ClkCnt_Q3 & ClkCnt_Q3) begin
ClkCnt_Q3 <= 3'd1;
end else begin
ClkCnt_Q3 <= ClkCnt_Q3 + 3'd1;
end
Pclk_Q <= (SysCmdValue_Q)?1'b0:ClkCnt_Q3;
DotClkEn_Q <= ((~ClkCnt_Q3) & ClkCnt_Q3 & ClkCnt_Q3);
end
end
/*
--外部接口在RD及CS低电平期间输出内部数据
--RS为0时输出忙信号.RS为1时输出当前地址的内部数据
*/
always @(SysRst or ExBusOut_Q or WrEn_Q or ExCs or ExRs or ExWr or ExRd)
begin
if (!SysRst) begin
ExOutM = 16'bzzzzzzzzzzzzzzzz;
end else begin
if ((~ExCs) & ExWr & (~ExRd)) begin
ExOutM = (ExRs)?ExBusOut_Q:({15'd0,WrEn_Q});
end else begin
ExOutM = 16'bzzzzzzzzzzzzzzzz;
end
end
end
/*
--外部异步WR写入数据.
*/
always @(posedge ExWr or negedge SysRst)
begin
if (!SysRst) begin
WriteRgb_Q = 16'd0;
ExWrClk_Q= 1'b0;
RegAddr_Q= 3'd0;
end else begin
if (!ExCs) begin
if (!ExRs) begin
RegAddr_Q <= ExDataBus;
end else begin
WriteRgb_Q <= ExDataBus;
ExWrClk_Q <= ~ExWrClk_Q;
end
end
end
end
/*
--外部异步RD读出数据.
*/
always @(negedge ExRd or negedge SysRst)
begin
if (!SysRst) begin
ExRsR_Q = 1'b0;
ExCsR_Q = 1'b1;
end else begin
ExCsR_Q <= ExCs;
ExRsR_Q <= ExRs;
end
end
always @(posedge ExRd or negedge SysRst)
begin
if (!SysRst) begin
ExRdClk_Q = 1'b0;
end else begin
if((~ExCsR_Q) & ExRsR_Q) begin
ExRdClk_Q <= ~ExRdClk_Q;
end
end
end
/*
--主时钟打两拍同步采用外部读写信号
*/
always @(posedge Clk54 or negedge SysRst)
begin
if (!SysRst) begin
ExRdClk_Q1 = 1'b0;
ExRdClk_Q2 = 1'b0;
ExRdClk_Q3 = 1'b0;
ExWrClk_Q1 = 1'b0;
ExWrClk_Q2 = 1'b0;
ExWrClk_Q3 = 1'b0;
end else begin
ExRdClk_Q1 <= ExRdClk_Q;
ExRdClk_Q2 <= ExRdClk_Q1;
ExRdClk_Q3 <= ExRdClk_Q2;
ExWrClk_Q1 <= ExWrClk_Q;
ExWrClk_Q2 <= ExWrClk_Q1;
ExWrClk_Q3 <= ExWrClk_Q2;
end
end
always @(posedge Clk54 or negedge SysRst)
begin
if (!SysRst) begin
InBusOut_Q= 16'd0;
ExBusOut_Q= 16'd0;
XRegValue_Q = 9'd0;
YRegValue_Q = 9'd0;
SysCmdValue_Q = 16'b0110000000000000;
WrEn_Q = 1'b0;
RamWeReg_Q = 1'b1;
RamTriState_Q = 1'b1;
RGB_Q = 16'd0;
FillCount_Q = 3'd7;
BRGBValue_Q= 16'd0;
FRGBValue_Q= 16'd0;
RamAddrBus_Q = 18'd0;
RamCsReg_Q = 1'b1;
PrePareData = 16'd0;
end else begin
if ((( ExRdClk_Q3) & (~ExRdClk_Q2) & (~ExRdClk_Q1)) |
((~ExRdClk_Q3) & ( ExRdClk_Q2) & ( ExRdClk_Q1))) begin
IncAddr = 1'b1;
end else begin
IncAddr = 1'b0;
end
if ((( ExWrClk_Q3) & (~ExWrClk_Q2) & (~ExWrClk_Q1)) |
((~ExWrClk_Q3) & (ExWrClk_Q2) & ( ExWrClk_Q1))) begin
AskWr = 1'b1;
end else begin
AskWr = WrEn_Q;
end
XRegOver = (XRegValue_Q == 9'b111011111)?1'b1:1'b0;
YRegOver = (YRegValue_Q == 9'b100001111)?1'b1:1'b0;
PrePareData = WriteRgb_Q;
IndexData = WriteRgb_Q;
InRamWe = 1'b1;
if (!ClkCnt_Q3) begin
if (AskWr) begin
case (RegAddr_Q)
3'b000:begin
XRegValue_Q <= PrePareData;
WrEn_Q <= 1'b0;
end
3'b001:begin
YRegValue_Q <= PrePareData;
WrEn_Q <= 1'b0;
end
3'b100:begin
FRGBValue_Q <= PrePareData;
WrEn_Q <= 1'b0;
end
3'b101:begin
BRGBValue_Q <= PrePareData;
WrEn_Q <= 1'b0;
end
3'b110:begin
SysCmdValue_Q <= PrePareData;
WrEn_Q <= 1'b0;
end
3'b010:begin
InRamWe = 1'b0;
IncAddr = 1'b1;
WrEn_Q <= 1'b0;
end
3'b011:begin
if (!IndexData) begin
PrePareData = BRGBValue_Q;
InRamWe = SysCmdValue_Q;
end else begin
PrePareData = FRGBValue_Q;
InRamWe = 1'b0;
end
IncAddr = 1'b1;
WrEn_Q <= (FillCount_Q | FillCount_Q | FillCount_Q);
FillCount_Q <= FillCount_Q + 3'd7;
end
3'b111:begin
if (FillHead_Q) begin
IncAddr = 1'b1;
InRamWe = 1'b0;
if (YRegOver & XRegOver) begin
WrEn_Q <= 1'b0;
end
end else begin
WrEn_Q <= 1'b1;
end
end
endcase
end
RGB_Q <= (SysCmdValue_Q)?16'd0:RamDataBus;
SramAddr = YRegValue_Q;
SramAddr = XRegValue_Q;
RamAddrBus_Q <= XRegValue_Q;
RamAddrBus_Q <= SysCmdValue_Q;
end else begin
if (AskWr) begin
WrEn_Q <= 1'b1;
end
ExBusOut_Q <= RamDataBus;
SramAddr = HsCount_Q;
SramAddr = DotCount_Q;
RamAddrBus_Q <= DotCount_Q;
RamAddrBus_Q <= SelDispRam_Q;
end
InBusOut_Q <= PrePareData;
RamTriState_Q <= InRamWe;
RamWeReg_Q <= InRamWe;
SramAddr = SramAddr - {4'd0,SramAddr};
RamAddrBus_Q <= SramAddr;
/*根据配置字调整XY*/
if (IncAddr) begin
case (SysCmdValue_Q)
3'b001:begin
if (XRegOver) begin
XRegValue_Q <= 9'd0;
end else begin
XRegValue_Q <= XRegValue_Q + 9'd1;
end
end
3'b011:begin
if (XRegOver) begin
XRegValue_Q <= 9'd0;
if (YRegOver) begin
YRegValue_Q <= 9'd0;
end else begin
YRegValue_Q <= YRegValue_Q + 9'd1;
end
end else begin
XRegValue_Q <= XRegValue_Q + 9'd1;
end
end
3'b110:begin
if (YRegOver) begin
YRegValue_Q <= 9'd0;
end else begin
YRegValue_Q <= YRegValue_Q + 9'd1;
end
end
3'b111:begin
if (YRegOver) begin
YRegValue_Q <= 9'd0;
if (XRegOver) begin
XRegValue_Q <= 9'd0;
end else begin
XRegValue_Q <= XRegValue_Q + 9'd1;
end
end else begin
YRegValue_Q <= YRegValue_Q + 9'd1;
end
end
default:begin
end
endcase
end
RamCsReg_Q <= SysCmdValue_Q;
end
end
/*--产生TFT行同步*/
always @(posedge Clk54 or negedge SysRst)
begin
if (!SysRst) begin
DotCount_Q = 9'd0;
DsState_Q = 2'd0;
DsMark = 1'b0;
end else begin
if (DotClkEn_Q) begin
case (DsState_Q)
2'd0:/*=>--41 相当于<= 40*/
DsMark = (DotCount_Q & DotCount_Q);
2'd1:/*when "01" =>--2 相当于<= 1*/
DsMark = DotCount_Q;
2'd2:/*=>--480 相当于<= 479*/
DsMark = (DotCount_Q & DotCount_Q & DotCount_Q & DotCount_Q &
DotCount_Q & DotCount_Q & DotCount_Q & DotCount_Q);
2'd3:/*--2 相当于<= 1*/
DsMark = DotCount_Q;
endcase
DsState_Q <= DsState_Q + {1'b0,DsMark};
DotCount_Q <= (DsMark)?9'd0:(DotCount_Q + 9'd1);
end
end
end
/*--产生TFT帧同步信号*/
always @(posedge Clk54 or negedge SysRst)
begin
if (!SysRst) begin
DE_Q= 1'b0;
end else begin
DE_Q <= (SysCmdValue_Q)?1'b0:(HsState_Q & (~HsState_Q) & DsState_Q & (~DsState_Q));
end
end
/*--产生帧同步时钟*/
always @(posedge Clk54 or negedge SysRst)
begin
if (!SysRst) begin
HsCount_Q = 9'd0;
HsState_Q = 2'd0;
FillHead_Q = 1'b0;
SelDispRam_Q = 1'b0;
LedCount_Q = 5'd0;
end else begin
if (DsState_Q & DsState_Q & DotCount_Q & DotClkEn_Q) begin
case (HsState_Q)
2'd0:/*--10相当于<= 9*/
HsMark = (HsCount_Q & HsCount_Q);
2'd1:/*--2相当于<= 1*/
begin
HsMark = HsCount_Q;
FillHead_Q <= (RegAddr_Q & RegAddr_Q & RegAddr_Q & WrEn_Q);
SelDispRam_Q <= SysCmdValue_Q;
end
2'd2:/*--272相当于<= 271*/
HsMark = (HsCount_Q & HsCount_Q & HsCount_Q & HsCount_Q & HsCount_Q);
2'd3:/*--2相当于<= 1*/
HsMark = HsCount_Q;
endcase
HsState_Q <= HsState_Q + {1'b0,HsMark};
HsCount_Q <= (HsMark)?9'd0:(HsCount_Q + 9'd1);
LedCount_Q <= LedCount_Q + 5'd1;
end
end
end
/*LED调光进程*/
always @(posedge Clk54 or negedge SysRst)
begin
if (!SysRst) begin
LedOn_W = 1'b0;
LedOn_Q = 1'b0;
end else begin
case (SysCmdValue_Q)
3'd0:
LedOn_W = 1'b0;
3'd1:
LedOn_W = (LedCount_Q < 5'd8)?1'b1:1'b0;
3'd2:
LedOn_W = (LedCount_Q < 5'd12)?1'b1:1'b0;
3'd3:
LedOn_W = (LedCount_Q < 5'd16)?1'b1:1'b0;
3'd4:
LedOn_W = (LedCount_Q < 5'd20)?1'b1:1'b0;
3'd5:
LedOn_W = (LedCount_Q < 5'd24)?1'b1:1'b0;
3'd6:
LedOn_W = (LedCount_Q < 5'd28)?1'b1:1'b0;
default:
LedOn_W = 1'b1;
endcase
// LedOn_Q <= (SysCmdValue_Q)?1'b0:LedOn_W;
LedOn_Q <=SysCmdValue_Q;
end
end
endmodule 小白有一事不明,你用的液晶屏就是一般MCU驱动的那种里面带驱动芯片的屏还是只有液晶面板没有驱动芯片的屏 不带总线型驱动芯片的屏 还有板子吗?买一块 mark mark 收藏一下! 回复【30楼】jobwork 无业游侠
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也就是单独一个屏幕不带任何芯片了?? 这种屏怎么控制显示东西啊,LZ厉害, 小弟只会扫数码管~~~ 泼水…
但凡做类似东西的人,都是自起炉灶,自画电路自行布板,代码更是如出一辙,结果也多是不了了之
建议:尽可能共用一套电路一套PCB,大家共同做一个项目,这样才有积累,才有真正的提高!更为关键的是,出了问题才好解决,才更能充分体现出本坛乐于共享交流的初衷。
这个方案自己做可行性不大,成本难以控制且货源复杂,楼上核算的成本太过天真,批量生产时会凸现出很多问题,尤其是新手,绝不建议拿公_款做这类带有一定实验性质的事,当然,除非老板心甘情愿… 学习下,谢谢楼主。 上班了再细看 回复【30楼】jobwork 无业游侠
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也就是单独一个屏幕不带任何芯片了?? 这种屏怎么控制显示东西啊,lz厉害, 小弟只会扫数码管~~~
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电路板背面有芯片的,nios 控制的
回复【36楼】Totry
泼水…
但凡做类似东西的人,都是自起炉灶,自画电路自行布板,代码更是如出一辙,结果也多是不了了之
建议:尽可能共用一套电路一套pcb,大家共同做一个项目,这样才有积累,才有真正的提高!更为关键的是,出了问题才好解决,才更能充分体现出本坛乐于共享交流的初衷。
这个方案自己做可行性不大,成本难以控制且货源复杂,楼上核算的成本太过天真,批量生产时会凸现出很多问题,尤其是新手,绝不建议拿公_款做这类带有一定实验性质的事,当然,除非老板心甘情愿…
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没理解你说的意思,我做这个是在学习,什么自起炉灶,批量生产,根本谈不上,只是给单位产品做个检测装备 mark 关注 在做这方面的事情 mark ok 回复【39楼】jobwork 无业游侠
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maxII 能用nios? mark 感谢楼主 回复【43楼】McuY
回复【39楼】jobwork 无业游侠
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maxii 能用nios?
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不好意思,我没表达清楚
maxii做的屏驱动8088总线的,我说的背面有芯片,说的是我电路板背面还有一个ep3c10最小系统板跑的是NIOS, 楼主辛苦了 mark mark~~学习~ mark.学习了。 还有10快空板,用上面贴出的代码就可以驱动,原理图在楼主位
有学这个的联系,grpmcu@163.com mark MARK mark!! 楼主 请问您有这个板子的PCB文件吗? 可否上传一个,谢谢! 顶下 用arm省事 回复【28楼】jobwork 无业游侠
这是全部代码,de驱动,hsync 固定低电平
感谢widesoft2 通关的代码原帖
http://www.ourdev.cn/bbs/bbs_content.jsp?bbs_sn=4799753&bbs_page_no=1&search_mode=3&search_text=widesoft2&bbs_id=1029
/*
接口说明:
clk54:系统晶振,选择54m晶振
sysrst:系统复位线.
exdatabus:外部16位数据总线
excs:控制器片选,
exrs:数据批令选择
exwr:写信号
exrd:读信号
ramaddrbus:显存地址线.
ramdatabus:显存数据总线
ramcs:显存片选
ramwe:显存写选通.
ledon:背光控制pwm
de:tft屏
de:vsynctft屏,
hsy......
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那位大侠能把寄存器注一下,写RAM的部份看不太懂 回复【28楼】jobwork 无业游侠
这是全部代码,de驱动,hsync 固定低电平
感谢widesoft2 通关的代码原帖
http://www.ourdev.cn/bbs/bbs_content.jsp?bbs_sn=4799753&bbs_page_no=1&search_mode=3&search_text=widesoft2&bbs_id=1029
/*
接口说明:
clk54:系统晶振,选择54m晶振
sysrst:系统复位线.
exdatabus:外部16位数据总线
excs:控制器片选,
exrs:数据批令选择
exwr:写信号
exrd:读信号
ramaddrbus:显存地址线.
ramdatabus:显存数据总线
ramcs:显存片选
ramwe:显存写选通.
ledon:背光控制pwm
de:tft屏
de:vsynctft屏,
hsy......
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那位大侠能把寄存器注一下,写RAM的部份看不太懂 mark. 持续关注此帖。等待审核。都注_册好几次了 今天看有网友能利用我的代码,点亮TFT屏,心里比较高兴。在论坛上学会了AVR的GCC,这段代码也算是回馈论坛了。 mark mark 资料不错 MARK 顶 没有讲解 只有代码 郁闷...... library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity pll4f is
port (
signal CLK : IN STD_LOGIC;
signal STAUSCNT : BUFFER STD_LOGIC_VECTOR (2 DOWNTO 0)
);
end entity pll4f;
architecture pll4 of pll4f is
begin
process (CLK)
begin
IFCLK' EVENT AND CLK = '1' THEN
IF STAUSCNT = "110" THEN
STAUSCNT <= "001";
ELSE
STAUSCNT <= STAUSCNT+1;
END IF;
END IF;
end process;
end pll4;
请问不需要复位到 "001" 吗? 参考这个代码
http://www.ourdev.cn/bbs/bbs_content.jsp?bbs_sn=4534978&bbs_page_no=1&search_mode=1&search_text=tft&bbs_id=1029
process (Clk54,SysRst)
begin
if SysRst = '0' then
ClkCnt_3 <= "001";
Pclk <= '0';
DotClkEn <= '0';
elsif (Clk54'event and Clk54 = '1') then
if (ClkCnt_3(2) and ClkCnt_3(1)) = '1' then --到达状态11X时 重新计数
ClkCnt_3 <= "001";
else
ClkCnt_3 <= ClkCnt_3 + 1;
end if;
Pclk <= ClkCnt_3(2);
DotClkEn <= ((not ClkCnt_3(2)) and ClkCnt_3(1) and ClkCnt_3(0));
end if;
end process; mark, 学习... 公司用PowerPC处理器,没有LCD控制器,正需要用FPGA做一个,还没思路,正打算FPGA+SDRAM做,道路漫长啊,看别人的代码总是很痛苦的事情 mark~~~~ mark~~~~ Mark了。。。。。。 支持楼主的分享 酷帖。收下。多谢分享。 如果换成7,8寸屏的驱动呢 mark...................... 楼主做的挺好的,还有板子没,我买个玩下 我的QQ:104015445 不错,学习中 哈哈啊我也想做没时间 lhao2199 发表于 2012-4-20 23:20
如果换成7,8寸屏的驱动呢
都能驱动的吧? 本帖最后由 ljt80158015 于 2012-4-30 11:18 编辑
很好的学习资料!
其实直接用TFT控制器也挺好的,比如:ra8875 ljt80158015 发表于 2012-4-29 19:41 static/image/common/back.gif
很好的学习资料!
其实直接用TFT控制器也挺好的,比如:ra8875
ra8875比这个有优势 刚开始接触cpld,不太懂 mark!!!! mark!!!{:lol:} jobwork 发表于 2011-10-15 10:28 static/image/common/back.gif
通用的4.3寸TFT时序图
(原文件名:时序.jpg)
有点不明白DE模式,assign HSync = 1'b0;将Hsync拉低,根据时序图上,DE信号是输出信号,不对Hsync计数,在什么时候将它拉高呢? jobwork 发表于 2011-10-29 10:31 static/image/common/back.gif
回复【30楼】jobwork 无业游侠
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我顶你 LZ是完全用CPLD驱动没有驱动芯片的液晶屏么?
学习了~ 收藏一下! 以后会用上 gaoyu 发表于 2011-10-15 22:28 static/image/common/back.gif
问一下用FPGA中的程序在断电后会消失吗 是sof格式的 初学者多多指教哈
fpga断电后,会消失,因为是基于sram的 加油继续努力。。。。共同进步 MARK一下 做的不错,顶一个! MARK,有空的时候研究一下,正好有好多4.3的屏
mark cpld tft 4.3 driver 非常感谢楼主的分享
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