请教ABB TDM光通信的VERILOG实现。
我是个新手。由于工程需要,在FPGA上实现ABB TDM光通信的串并协议转换。请教各位前辈该如何设计改程序呢?http://cache.amobbs.com/bbs_upload782111/files_46/ourdev_684161ZXG5ZP.jpg
ABB TDM通信协议 (原文件名:2011-10-12 10 48 02.jpg)
自己写了一个程序,出现错误如下:“The logic for ** does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.”。我的程序如下:
module TDM32(clk,fstart,din,dout,rdy);
input clk;
input fstart;
input din;
output dout;
output rdy;
reg dout;
reg rdy;
reg data_temp;
reg counter;
reg en;
initial begin
counter<=32;
en<=0;
data_temp<=0;
end
always @(negedge fstart or posedge clk) begin
if(counter==32)begin
en<=1;
rdy<=0;
data_temp<=0;
end
else if(counter>0 && counter<=31)begin
data_temp<=(data_temp<<1);
data_temp<=din;
end
else if(counter==0)begin
en<=0;
dout<=data_temp;
counter<=32;
rdy<=1;
end
else begin
en<=0;
data_temp<=0;
counter<=32;
rdy<=0;
end
end
endmodule 发现是由于在always @语句中使用negedge fstart or posedge clk造成的。这种方式是不对的,应该怎么处理呢? 别沉了啊,怎么处理这种问题呢?各位前辈。 74164
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