VHDL的一道简单程序 怎么语法错了??
library IEEE;use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sa is
Port ( in1 : inSTD_LOGIC:='1';
in2 : inSTD_LOGIC:='1';
clk:in std_logic;
out2 : outSTD_LOGIC);
end sa;
architecture w of sa is
begin
process(clk)
begin
if (clk'event and clk='1') then
out2<=in1;
else
out2<='0';
end if;
end process;
end w; 显示的 错误是 :ERROR:Xst:827 - "F:/xilinx project/tttt/sa.vhd" line 44: Signal out2 cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release. out2是触发器,时钟上升沿时采样in1。 else的分支没法实现。
个人学习的体会,vhdl/verilog都是描述硬件电路结构的语言,每种结构的语法模板就那么几种。
很多貌似c语言的流程描述写法,都无法综合成电路实现。
不要把描述结构的语言当做c那样的描述流程的语言来理解。 学习了。。。。
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