VHDL 赋值语句位置差异
library ieee;use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity add_product is
port(
clk : in std_logic;
clock : in std_logic;
reset : in std_logic; -----enable '1'
outter : out std_logic_vector(9 downto 0);
initial_f : in std_logic_vector(9 downto 0);
en : in std_logic;
direction : in std_logic;
flag_out : out std_logic
);
end entity;
architecture behav of add_product is
signal flag : std_logic:='1';
signal flag1 : std_logic:='1';
signal flag1_reg : std_logic:='0';
signal direction_reg : std_logic:='0';
signal clear_flag1_reg : std_logic:='0';
signal clear_flag1 : std_logic:='0';
-- signal yx : std_logic:='1';
signal cnt : std_logic_vector(9 downto 0):="0000000000";
signal cnt_reg : std_logic_vector(9 downto 0):="0000000000";
-- signal num : std_logic_vector (3 downto 0):="0000";
begin
outter<=cnt;
flag_out<=flag;
flag1_reg<=flag1;
clear_flag1_reg<=clear_flag1;
--direction_reg<=direction; ----------1
process(clk)
begin
if clk'EVENT AND clk='1'then
if reset='1'then
flag1<='1';
elsif clear_flag1_reg='0' then
if en='1' andflag1='1' then
flag1<='0';
cnt_reg<=initial_f;
end if;
elsif clear_flag1_reg='1' then
flag1<='1';
end if;
end if;
end process;
counting:process(clock)
begin
if clock'EVENT AND clock='1'then
direction_reg<=direction; ------------2
if flag1_reg='0' then
cnt<=cnt_reg;
clear_flag1<='1';
elsif(flag=not direction_reg)then
if(cnt="1111111111") then
--flag<='0';
flag<=direction_reg;
else cnt<=cnt+1;
end if;
elsif(flag=direction_reg)then
if(cnt="0000000000") then
--flag<='1';
flag<=not direction_reg;
else cnt<=cnt-1;
end if;
end if;
end if;
end process counting;
end behav;
上面程序的1 跟 2 赋值语句有区别吗？怎么在实际应用中会有较大的差别呢？ --direction_reg<=direction; ----------1
这个是并行 可以说direction变化direction_reg同时也变化
direction_reg<=direction; ------------2
因为这个在进程里，只有clock上升沿到来之后才赋值给direction_reg，因此赋值次数clock频率有关。和clock不跳变的话就不会赋值。
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