VHDL语言
library ieee;use ieee.std_logic_1164.all;
entity decoder is
port(
ena:in std_logic;
sel:in integer range 0 to 7;
x:out std_logic_vector(4 downto 0));
end decoder;
architecture not_ok of decoder is
begin
process(ena,sel)
begin
if(ena='0')then
x<=(others=>'1');
else
x<=(sel=>'0',others=>'1');
end if;
end process;
end not_ok;
在巴西人写的书籍里有这么一个实列,m-n译码器,但在代码中x<=(sel=>'0',others=>'1')中存在缺陷,原因是sel不是局部静态信号
但该怎么修正呢?自己是菜鸟级的,望各位大侠指教……
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