VHDL程序求助
---- File : <filename>.vhd
-- Author : <author>
-- Date : <month>/<day>/<year>
-- Version : <major>.<minor>
-- Abstract : <description>
--
-- Modification History:
-- Date By Version Change Description
--
-- ===========================================================
-- 00/00/00 xxx x.x Original
--
-- ===========================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity shu255 is
port(
rst,clk : instd_logic ;
key : in std_logic_vector(7 downto 0);
dataout : out std_logic_vector(7 downto 0);
en : out std_logic_vector(7 downto 0)
);
end entity shu255;
architecture one of shu255 is
signal clock : std_logic;
signal keyvalue1 :std_logic_vector(7 downto 0);
signal keyvalue : integer range 0 to 255;
begin
keyvalue1<=key;
fenpin:process(rst,clk)
variable cnt1: integer range 0 to 1000;
variable cnt2: integer range 0 to 100;
begin
if(rst='0') then
cnt1:=0;
cnt2:=0;
elsif(rst='1'and rising_edge(clk)) then
if(cnt1=1000) then
cnt1:=0;
clock<=not clock;
elsif(cnt2=100) then
cnt2:=0;
cnt1:=cnt1+1;
else
cnt2:=cnt2+1;
end if;
end if;
end process fenpin;
process(keyvalue1,rst,clock)
--signal keyvalue : integer range 0 to 255;
variable cnt : integer range 0 to 2;
begin
keyvalue <= conv_integer(keyvalue1);
if(rst='0') then
keyvalue<=0;
cnt:=0;
elsif(rising_edge(clock)) then
if(cnt=2) then
cnt:=0;
else
cnt:=cnt+1;
end if;
end if;
scanwei:case cnt is
when 0 =>
baiwei:case (keyvalue/128) is -- hgfedcba
when 0 => en<="11011111";dataout<="11000000";
when 1 => en<="11011111";dataout<="11111001";
when 2 => en<="11011111";dataout<="10100100";
when others=> en<="11111111";dataout<="11111111";
end case baiwei;
when 1=>
shiwei:case ((keyvalue/8)rem 8) is
when 0 => en<="10111111";dataout<="11000000";
when 1 => en<="10111111";dataout<="11111001";
when 2 => en<="10111111";dataout<="10100100";
when 3 => en<="10111111";dataout<="10110000";
when 4 => en<="10111111";dataout<="10011001";
when 5 => en<="10111111";dataout<="10010010";
when 6 => en<="10111111";dataout<="10000010";
when 7 => en<="10111111";dataout<="11111000";
when 8 => en<="10111111";dataout<="10000000";
when 9 => en<="10111111";dataout<="10010000";
when others => en<="11111111";dataout<="11111111";
end case shiwei;
when 2=>
gewei:case (keyvalue rem 8) is
when 0 => en<="01111111";dataout<="11000000";
when 1 => en<="01111111";dataout<="11111001";
when 2 => en<="01111111";dataout<="10100100";
when 3 => en<="01111111";dataout<="10110000";
when 4 => en<="01111111";dataout<="10011001";
when 5 => en<="01111111";dataout<="10010010";
when 6 => en<="01111111";dataout<="10000010";
when 7 => en<="01111111";dataout<="11111000";
when 8 => en<="01111111";dataout<="10000000";
when 9 => en<="01111111";dataout<="10010000";
when others => en<="11111111";dataout<="11111111";
end case gewei;
when others =>
end case scanwei;
end process ;
end architecture one;
就是将拨码开关KEY 读回来的值
在数码管上显示
里面 有个位矢量转为十进制 和段码的程序。
现在出现了一个警告
@W: CL170 :"C:\ISPTOO~1\lc4256v\shu255\shu255.vhd":66:8:66:9|Pruning bit <6> of keyvalue(7 downto 0) - not in use ...
@W: CL112 :"C:\ISPTOO~1\lc4256v\shu255\shu255.vhd":45:9:45:10|Feedback mux created for signal clock. Did you forget the set/reset assignment for this signal?
@W: CL209 :"C:\ISPTOO~1\lc4256v\shu255\shu255.vhd":27:5:27:7|Input port bit <6> of key(7 downto 0) is unused
把一位的按键输入忽略了。
这个警告我要好好管理一下。
请高手帮忙一下 帮你小改一下。不知对不对。
用rem的话仿真能通过，但硬件不一定对。
clk2是动态扫描的时钟，控制在300HZ左右
clk全局时钟
rst 其实没什么用，
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity shu255 is
port(
rst,clk,clk2 : instd_logic ;
key : in integer range 0 to 255;
dataout : out std_logic_vector(7 downto 0);
en : out std_logic_vector(7 downto 0)
);
end entity shu255;
architecture one of shu255 is
SIGNALcnt : integer range 0 to 2;
begin
process(clk2)
begin
if(rising_edge(clk2)) then
if(cnt=2) then
cnt<=0;
else
cnt<=cnt+1;
end if;
end if;
end process ;
process(key,cnt,rst)
begin
if (rst='1')then
en<=(others=>'1');
dataout<=(others=>'1');
else
scanwei:case cnt is
when 0 =>
baiwei:case (key/128) is -- hgfedcba
when 0 => en<="11011111";dataout<="11000000";
when 1 => en<="11011111";dataout<="11111001";
when 2 => en<="11011111";dataout<="10100100";
when others=> en<="11111111";dataout<="11111111";
end case baiwei;
when 1=>
shiwei:case ((key/8)rem 8) is
when 0 => en<="10111111";dataout<="11000000";
when 1 => en<="10111111";dataout<="11111001";
when 2 => en<="10111111";dataout<="10100100";
when 3 => en<="10111111";dataout<="10110000";
when 4 => en<="10111111";dataout<="10011001";
when 5 => en<="10111111";dataout<="10010010";
when 6 => en<="10111111";dataout<="10000010";
when 7 => en<="10111111";dataout<="11111000";
when 8 => en<="10111111";dataout<="10000000";
when 9 => en<="10111111";dataout<="10010000";
when others => en<="11111111";dataout<="11111111";
end case shiwei;
when 2=>
gewei:case (key rem 8) is
when 0 => en<="01111111";dataout<="11000000";
when 1 => en<="01111111";dataout<="11111001";
when 2 => en<="01111111";dataout<="10100100";
when 3 => en<="01111111";dataout<="10110000";
when 4 => en<="01111111";dataout<="10011001";
when 5 => en<="01111111";dataout<="10010010";
when 6 => en<="01111111";dataout<="10000010";
when 7 => en<="01111111";dataout<="11111000";
when 8 => en<="01111111";dataout<="10000000";
when 9 => en<="01111111";dataout<="10010000";
when others => en<="11111111";dataout<="11111111";
end case gewei;
when others => null;
end case scanwei;
end if;
end process ;
end architecture one; 我试了一下 还是错误。
同样的警告。
页:
[1]