传说管脚镀金的SARONIX的100M有源晶振，外壳是接地还是接电源？
测试了一下，外壳是跟电源连接的，额，有缘晶振不是一般都接地吗？EPM7128SLC84-15的最大输入频率为多大？100M没问题吧，看手册上应该没问题啊... //water ledmodule water_led(clk,rst_n,led_out);
input clk;//clock
input rst_n;
output led_out;//water led output
reg led_tag = 1'b1;//status tag
reg counter = 1'b0;//counter
//division clock
always @(posedge clk)
begin
if(!rst_n) begin
counter <= 0;
led_tag <= 1'b1;
end
else
counter <= counter + 1'b1;
if(counter == 3'd5/*0_000_000*/) begin
led_tag = led_tag<<1'b1;
if(led_tag == 1'b0)
led_tag <= 1'b1;
counter <= 1'b0;
end
end
//assignment voluation
assign led_out = led_tag;
endmodule
这段小程序改改后，编译不过去
//water led
module water_led(clk,rst_n,led_out);
input clk;//clock
input rst_n;
output led_out;//water led output
reg led_tag = 1'b1;//status tag
reg counter = 1'b0;//counter
//division clock
always @(posedge clk,negedge rst_n)
begin
if(!rst_n) begin
counter <= 0;
led_tag <= 1'b1;
end
else
counter <= counter + 1'b1;
if(counter == 3'd5/*0_000_000*/) begin
led_tag = led_tag<<1'b1;
if(led_tag == 1'b0)
led_tag <= 1'b1;
counter <= 1'b0;
end
end
//assignment voluation
assign led_out = led_tag;
endmodule
提示：
Error (10200): Verilog HDL Conditional Statement error at water_led.v(17): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct
为啥子呢？ 100M的频率对于epm7128SL-15来说，有点高，反应不过来，换个40M的..
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