Verilog一道小题，有点意思
适合我这样的新手题目：
The example below models a flip-flop with asynchronous set/reset logic (active low).
The model synthesizes correctly, but there is a corner case where simulation results are incorrect.
What is the corner case?
always_ff @( posedge clk
or negedge rst_n // active-low reset
or negedge set_n // active-low set
)
if (!rst_n) // reset has priority over set
q_out <= ’0; // reset all bits to zero
else if (!set_n)
q_out <= ’1; // set all bits to one
else
q_out <= data_in; // d input assignment
来自：http://www.sutherland-hdl.com/ （题目就在主页上 2011年5月19日）
答案：http://www.sutherland-hdl.com/quiz-and-tips.php 回复【楼主位】Comedian
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确实很有价值 确实很有价值，这个网站看起来挺不错的~
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