提问:关于FPGA模拟UART串口的问题
程序如下:module UART
(
clk_48M,
rst,
TXD
);
input clk_48M;
input rst;
output TXD;
wire clk_144M;
reg state;
reg clk_115200;
reg count;
reg TXD;
reg TXDATA;
UARTPLL U0
(
.inclk0(clk_48M),
.c0(clk_144M)
);
always @ (posedge clk_144M or negedge rst)
begin
if (!rst)
begin
count<=0;
clk_115200<=0;
end
else
begin
if (count<625) //-------144M/115200=1250
count<=count+16'b1;
else
begin
count<=0;
clk_115200<=~clk_115200;
end
end
end
always @ (posedge clk_115200 or negedge rst)
begin
if (!rst)
begin
state<=0;
TXDATA<=43;
end
else
begin
if (state<10)
state<=state+4'b1;
else
begin
state<=0;
if ((TXDATA>42)&&(TXDATA<122))
TXDATA<=TXDATA+1;
else
TXDATA<=43;
end
end
end
always @ (state)
begin
case (state)
4'd0:TXD<=1'b1;
4'd1:TXD<=1'b0;
4'd2:TXD<=TXDATA;
4'd3:TXD<=TXDATA;
4'd4:TXD<=TXDATA;
4'd5:TXD<=TXDATA;
4'd6:TXD<=TXDATA;
4'd7:TXD<=TXDATA;
4'd8:TXD<=TXDATA;
4'd9:TXD<=TXDATA;
4'd10:TXD<=1'b1;
default:TXD<=1'b1;
endcase
end
endmodule
锁相环锁到144MHZ以后刚好能整除115200,停止位2,用超级终端(一行80个字符)来查看,程序中是80个字符循环显示,前面大概5秒左右均无法完整显示(有乱码),之后就能正常,按下RST也能一行一行对齐显示,为什么呢?是锁相环达到稳定之前的延迟吗?
还有,如果我想隔一段时间输出一个数,在state<10处改成<100等数(当然state的位数有修改),就会一直输出乱码,不解中…… 关注 果断的插核 ,用 chipscope之类的片上逻辑仪抓波形分析 原来这就是锁相环啊!!
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