请大家帮忙看看是不是频率太高了？无法跳出idle状态。
大家好，请教一个问题，以下代码目的是通过检测ledl_en这个变量，一旦发生变化，即pos_edge有效时出发状态机送出数据，但是在板上实验发现无法运行，使用晶振为50M的，我怀疑是pos_edge问题，因为我把
case(c_state)
idle:
begin
cs = 1'b0;
wr = 1'b0;
if((~busy)&pos_edge)
n_state = bety0_start;
改成
case(c_state)
idle:
begin
cs = 1'b0;
wr = 1'b0;
if(~busy)
n_state = bety0_start;
就会运行。也许大家说可能led_en没有变化，所以状态没改变，但是我使用示波器或者其他手段测试，确定是有运行的，很大可能是不是晶振频率太高了？但是我调低了也没有变化。
请大家帮我看看怎么解决，谢谢大家。
reg reg_1, reg_2;
always @(posedge clk, posedge rst)
if(rst)
begin
reg_1 <= 0;
reg_2 <= 0;
end
else
begin
reg_1 <= led_en;
reg_2 <= reg_1;
end
wire pos_edge = (reg_1 != reg_2); // now we can detect de_clk rising edges
assign edge_h = pos_edge;
reg c_state, n_state;
always @(posedge clk, posedge rst)
if(rst)
c_state <= idle;
else
c_state <= n_state;
always @(*)
case(c_state)
idle:
begin
cs = 1'b0;
wr = 1'b0;
if((~busy)&pos_edge)
n_state = bety0_start;
end
bety0_start:
begin
cs = 1'b1;
wr = 1'b1;
out_data = 8'h41;
n_state = bety0_end;
end
bety0_end:
begin
cs = 1'b0;
wr = 1'b0;
if(~busy)
n_state = bety1_start;
end
bety1_start:
begin
cs = 1'b1;
wr = 1'b1;
out_data = 8'h01;
n_state = bety1_end;
end
bety1_end:
begin
cs = 1'b0;
wr = 1'b0;
if(~busy)
n_state = bety2_start;
end
bety2_start:
begin
cs = 1'b1;
wr = 1'b1;
out_data = reg_dat;
n_state = bety2_end;
end
bety2_end:
begin
cs = 1'b0;
wr = 1'b0;
if(~busy)
n_state = bety3_start;
end
bety3_start:
begin
cs = 1'b1;
wr = 1'b1;
out_data = 8'h41;
n_state = bety3_end;
end
bety3_end:
begin
cs = 1'b0;
wr = 1'b0;
if(~busy)
n_state = bety4_start;
end
bety4_start:
begin
cs = 1'b1;
wr = 1'b1;
out_data = 8'h02;
n_state = bety4_end;
end
bety4_end:
begin
cs = 1'b0;
wr = 1'b0;
if(~busy)
n_state = bety5_start;
end
bety5_start:
begin
cs = 1'b1;
wr = 1'b1;
out_data = reg_dat;
n_state = bety5_end;
end
bety5_end:
begin
cs = 1'b0;
wr = 1'b0;
if(~busy)
n_state = idle;
end
default: n_state = idle;
endcase
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