CPLD关于变量不能赋值的问题！！帮忙看一下。
我觉得发代码来问问题是一件比较麻烦的一件事情。不过没源代码又不知怎么描述这么奇怪的一个问题。全贴出来吧，希望大家能指点一下。这个原本是想做一个24进制的计数器，稍做修改就能实现可变模。但是就在十六进制数转成数码管显示的时候出现了一点问题。下面那个datashi的变量赋值无效。只有datage行。工程文件（Quartus II 4.1写的。）也上传了。刚学VHDL，还不是很习惯，经常会带进C语言的思想，大家指导一下。谢谢！counter.rarourdev_638307Q7UGSC.rar(文件大小:164K) (原文件名:counter.rar)
（这个与附件一样的方便大家：http://u.115.com/file/bhd7h1pr）
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port (clk,rst,en,load: in std_logic;
segduan : out std_logic_vector(6 downto 0); --段选
segwei: out std_logic_vector(3 downto 0); --位选
setdata : in std_logic_vector(5 downto 0)); --置数输入
end entity counter;
architecture cnter of counter is
signal bcddspd : std_logic_vector(3 downto 0); --BCD码段显示
signal cntclk1 : std_logic_vector(4 downto 0); --数时钟
signal q : std_logic_vector(5 downto 0); --计数
begin
p_ctclk:process (clk)
begin
if (clk'event and clk='1')then
if cntclk1 = 31 then cntclk1 <= "00000";
else cntclk1<=cntclk1+1;
end if;
end if;
end process p_ctclk;
p_cnt:process(cntclk1(4),rst,en,load) begin --计数器
if rst='0' then q<=(others=>'0');
elsif cntclk1(4)'event and cntclk1(4)='1' then
if en ='1' then
if (load='0')then q<=setdata; else
if q<24 then q<=q+1;
else q<=(others=>'0');
end if;
end if;
end if;
end if;
end process p_cnt;
p_cvt:process (q,clk,rst)
variable datage,datashi:std_logic_vector(3 downto 0);
begin
if (clk'event and clk='1')then
--转换数码管显示
-- datage:=q(3 downto 0);
datage:='0'&'0'&q(5 downto 4);
-- datashi:='0'&'0'&q(5 downto 4);
-- if datashi>"1001" then
-- datashi:=datashi-"1010";
-- datage:=datage+'1';
-- end if;
-- if datage>"1001" then
-- datage:=datage-"1010";
-- end if;
end if;
-- if(rst = '0')then --复位清零
-- segwei<="0000";
-- elsif clk = '1' then segwei<="0001";bcddspd<=datage;
-- else segwei<="0010";bcddspd<=datashi;
-- end if;
end process p_cvt;
p_dspd:process(bcddspd) begin
case bcddspd is --送段选数据
when "0000" => segduan<="0111111"; when "0001" => segduan<="0000110";
when "0010" => segduan<="1011011"; when "0011" => segduan<="1001111";
when "0100" => segduan<="1100110"; when "0101" => segduan<="1101101";
when "0110" => segduan<="1111101"; when "0111" => segduan<="0000111";
when "1000" => segduan<="1111111"; when "1001" => segduan<="1101111";
when "1010" => segduan<="1110111"; when "1011" => segduan<="1111100";
when "1100" => segduan<="0111001"; when "1101" => segduan<="1011110";
when "1110" => segduan<="1111001"; when "1111" => segduan<="1110001";
when others => segduan<="0000000";
end case;
end process p_dspd;
end architecture cnter;
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