ads7825调试问题
为什么调试ADS7825时，能启动转换（即busy能变低再变高），可是读出的数据总是FF，这是为什么？有没有做过的人知道？或者遇到过同样问题的人交流一下。QQ：983482673 先买了两块ADS7825，然后用FPGA驱动他转换，通过CY68013传到上位机上看转换结果，结果总是0XFF，而量AD芯片数据出口有事0电压，我想可能是数据出口出于高阻态了。我调了几天，改了很多次程序，最终觉得是不是芯片有问题……决定再重新买两块芯片……（用的是ADS7825的双列直插式，好贵，心疼啊），买回来后发现还是一样的情况，真悲剧啊……而且当我换芯片的时候发现，不插AD转换芯片是一样的结果，啊……真的不知道这是什么个情况……现在就真的快要黔驴技穷了，曾找过原因是，不知道FPGA和ADS7825间需要不需要加3.3V电平到5V逻辑电平的转换芯片，但我看datasheet里面的VIH,VIL,VOH,VOL应该是兼容的啊……天啊，不知道怎么办了。
我测试时的程序是为了避免这种情况是自己的程序造成的，所以那个FPGA的VHDL程序是从网上一个论坛上花钱下的，基本没改，附在后面大家参考。电路是按照ADS7825datasheet里面第一个电路图连接的，CS接地，PAR/SER接5V，POWRD和PONC接地，用的是并行方式。测试的是同道1，接的5V电平，转换结果应该是0x4000。
真的不知道怎么办了，搞了两周了，有没有用过这个芯片的高手指点一下……谢谢。
VHDL程序如下：
-- Target Device:Spartan-IIE-300
-- Tool versions:ISE 7.1i
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ADS7825_control is
generic (
-- Destination minimal tick time 40 ns
-- 66 MHz --> 3 counts, 45 ns
-- 50 MHz --> 2 counts, 40 ns
--8 Mhz --> 1 counts, 125 ns
TICK_COUNT : integer := 3
);
port (
clk : in std_logic;
reset : in std_logic;
oe : in std_logic;
addr : in std_logic_vector(1 downto 0);
data : out std_logic_vector(15 downto 0);
rc : out std_logic; -- Read (1) / Convert (0)
busy : in std_logic; -- Busy flag (0)
byte : out std_logic; -- 8-Byte MSB (0) / LSB (1)
par : out std_logic; -- Paralel (1) / Serial (0)
ad : out std_logic_vector(1 downto 0);
db : in std_logic_vector(7 downto 0) -- Data in byte
);
end ADS7825_control;
architecture rtl of ADS7825_control is
constant Busy_wait : integer := 1050; -- Assume a tick for 40 ns, maximum busy time is 21 us
constant Byte_wait : integer := 8; -- Byte wait for more than 83 ns
constant AddressValid_wait : integer := 24; -- Address Valid wait for more than 500 ns
signal tick_reg : integer range 0 to TICK_COUNT - 1;
signal count_tick_reg : integer range 0 to Busy_wait;
signal rc_reg : std_logic;
signal byte_reg : std_logic;
signal busy_reg : std_logic;
type GLOBAL_TYPE is (PREPARE, RCSIGNAL, WAITBUSY, HIGHBYTE, LOWBYTE, DONE);
signal global_reg : GLOBAL_TYPE;
type DATA_TYPE is array(3 downto 0) of std_logic_vector(15 downto 0);
signal data_reg : DATA_TYPE;
signal count_data : integer range 0 to 3;
begin
process (clk, reset)
begin
if (reset='0') then
rc_reg <= '1';
byte_reg <= '0';
tick_reg <= 0;
busy_reg <= '0';
count_data <= 0;
elsif (clk'event and clk='1') then
tick_reg <= tick_reg + 1;
if (tick_reg = 0) then
case global_reg is
when PREPARE =>
count_data <= 0;
rc_reg <= '1'; -- Initialization
global_reg <= RCSIGNAL;
when RCSIGNAL =>
byte_reg <= '0';
rc_reg <= '0'; -- Start conversion
busy_reg <= '1';
global_reg <= WAITBUSY;
when WAITBUSY =>
rc_reg <= '1';
if (count_tick_reg = Busy_wait) then -- Waiting too long
count_tick_reg <= 0;
global_reg <= PREPARE;
elsif (busy = '1' and busy_reg = '0') then -- Busy off
count_tick_reg <= 0;
global_reg <= HIGHBYTE;
else -- Busy
count_tick_reg <= count_tick_reg + 1;
end if;
busy_reg <= busy;
when HIGHBYTE =>
if (count_tick_reg = Byte_wait) then -- Wait for more than 83 ns
count_tick_reg <= 0;
global_reg <= LOWBYTE;
if (count_data = 0) then
data_reg(3)(15 downto 8) <= db;
else
data_reg(count_data-1)(15 downto 8) <= db;
end if;
byte_reg <= '1';
else
count_tick_reg <= count_tick_reg + 1;
end if;
when LOWBYTE =>
if (count_tick_reg = Byte_wait) then -- Wait for more than 83 ns
count_tick_reg <= 0;
global_reg <= DONE;
if (count_data = 0) then
data_reg(3)(7 downto 0) <= db;
else
data_reg(count_data-1)(7 downto 0) <= db;
end if;
byte_reg <= '0';
count_data <= count_data + 1;
else
count_tick_reg <= count_tick_reg + 1;
end if;
when DONE =>
if (count_tick_reg = AddressValid_wait) then -- Wait for more then 500 ns
global_reg <= RCSIGNAL;
count_tick_reg <= 0;
else
count_tick_reg <= count_tick_reg + 1;
end if;
when others =>
global_reg <= PREPARE;
end case;
end if;
end if;
end process;
rc <= rc_reg when oe='0' else 'Z';
byte <= byte_reg when oe='0' else 'Z';
par<= '1' when oe='0' else 'Z';
ad <= CONV_STD_LOGIC_VECTOR(count_data,2) when oe='0' else (others => 'Z');
data <= data_reg(CONV_INTEGER(addr)) when oe='0' else (others => 'Z');
end rtl;
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