求把这几行代码转成VHDL!谢谢
module PDIUSBD12(//Alvalon-MM Slave
input cpu_rd,
input cpu_wr,
input cpu_cs,
input cpu_addr,
input cpu_wr_dat,
output cpu_rd_dat,
input cpu_be,
//Conduit End
//pdiusbd12 interface
output d12_rd,
output d12_wr,
output d12_cs,
output d12_addr,
inout d12_dat
);
/*****************************************/
assign d12_rd = cpu_rd | cpu_be;
assign d12_wr = cpu_wr | cpu_be;
assign d12_cs = cpu_cs;
assign d12_addr = cpu_addr;
assign d12_dat = (!d12_cs && !d12_wr) ? cpu_wr_dat : 8'hzz;
assign cpu_rd_dat = (!cpu_cs && !cpu_rd) ? d12_dat : 8'hzz;
endmodule library ieee;
use ieee.std_logic_1164.all;
entity PDIUSBD12 is
port(
--Alvalon-MM Slave
cpu_rd : in std_logic;
cpu_wr : in std_logic;
cpu_cs : in std_logic;
cpu_addr : in std_logic;
cpu_wr_dat : in std_logic_vector(7 downto 0);
cpu_rd_dat : out std_logic_vector(7 downto 0);
cpu_be : in std_logic_vector(3 downto 0);
--Conduit End
--pdiusbd12 interface
d12_rd : out std_logic;
d12_wr : buffer std_logic;
d12_cs : buffer std_logic;
d12_addr : out std_logic;
d12_dat : inout std_logic_vector(7 downto 0)
);
end;
architecture behav of PDIUSBD12 is
begin
d12_rd <= cpu_rd or cpu_be(0);
d12_wr <= cpu_wr or cpu_be(0);
d12_cs <= cpu_cs;
d12_addr <= cpu_addr;
d12_dat <=cpu_wr_dat when(not(d12_cs) and not(d12_wr)) = '1' else
null;
cpu_rd_dat <= d12_dat when(not(cpu_cs) and not(cpu_rd)) = '1' else
null;
end;
页:
[1]