FPGA中的信号诡异现象，求高手指点！
麻烦高手帮我看一下这个程序（附在下面），仿真时我把plagb_full_n一直设为高电平，plagc_empty_n一直设为低电平，clk时钟周期设为20ns，但是data口总是0,2,4,6……这样的递增，可是我在程序里明明是让它0,1,2,3,4……这样每次递增1啊，这是为什么呢？另外我想问一下，如果进程执行过程中，敏感信号又变化了，进程还没执行完，会不会重新复位，还是等到进程执行完了再回到进程开始处？
LIBRARY ieee;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_1164.all;
entity sram is
generic
(
IDLE : INTEGER := 0;
STATE1: INTEGER := 1;
STATE2: INTEGER := 2;
STATE3: INTEGER := 3;
STATE4: INTEGER := 4;
DELAY0: INTEGER := 5;
DELAY1: INTEGER := 6
);
port
(
-- Input ports
clk : inSTD_LOGIC;
plagb_full_n : inSTD_LOGIC;
plagc_empty_n : inSTD_LOGIC;
-- Output ports
slwr_n : out STD_LOGIC;
data : out STD_LOGIC_VECTOR(7 DOWNTO 0);
fifoaddr : out STD_LOGIC_VECTOR(1 DOWNTO 0);
pktend_n : out STD_LOGIC
);
end sram;
architecture arc_sram of sram is
-- Declarations (optional)
SIGNAL delay: INTEGER:=0 ;
SIGNAL cstate,nstate: INTEGER:=IDLE;
SIGNAL data_r: STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
SIGNAL fifoaddr_r: STD_LOGIC_VECTOR(1 DOWNTO 0):="10";
SIGNAL slwr_n_r: STD_LOGIC:='1';
begin
PROCESS(clk,cstate,plagb_full_n,plagc_empty_n)
BEGIN
IF (clk'EVENT AND clk='1') THEN
cstate<=nstate;
CASE cstate IS
WHEN IDLE=>
data<="00000000";
pktend_n<='1';
fifoaddr<="10";
IF( plagc_empty_n='0')THEN
nstate<=STATE1;
ELSE nstate<=IDLE;
END IF;
WHEN STATE1=>fifoaddr<="10";
nstate<=STATE2;
WHEN STATE2=>
IF( plagb_full_n='1') THEN
slwr_n<='1';
delay<=0;
nstate<=STATE3;
ELSE nstate<=IDLE;
END IF;
WHEN STATE3=> data<=data_r;
slwr_n<='0';
nstate<=DELAY0;
WHEN DELAY0=> delay<=delay+1;
nstate<=DELAY1;
WHEN DELAY1=>IF(delay=2) THEN
slwr_n<='1';
nstate<=STATE4;
ELSE nstate<=DELAY0;
END IF; //DELAY0和DELAY1起到延时作用再进入STATE4
WHEN STATE4=>data_r<=data_r+1;//明明每次递增1
nstate<=STATE2;
WHEN others=>nstate<=IDLE;
END CASE;
END IF;
END PROCESS;
end arc_sram;
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