做xinlinx公司的官方的第七期个实验时,神奇错误
将SDRAM挂在PLB总线上. 我建立一个PLB到OPB的桥,将SDRAM挂在OPB上.报错:ERROR:MDT - IPNAME:opb_v20 INSTANCE:opb_v20_0 PORT:OPB_Clk -
D:\softset\Xinlix\EDK\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mpd line 50 - ASSIGNMENT=REQUIRE is defined in the MPD. You must specify a connection in the MHS.
MPD文件中的语句如下:PORT SYS_Rst = "", DIR = I, ASSIGNMENT = REQUIRE .不知道怎么改,烦了2天了. 我尝试将ASSIGNMENT = REQUIRE 删除,又出现新的错误. 因为这个文件时软件系统的文件,应该没错. 请教,错误出在哪个环节. 坐等 交流 快来啦 啊听学姐说打补丁可以 可是打补丁后,还是没有解决问题撒 为什么没人回帖呢
hello.
Actually the parameters in your IP are directly cross checked with the MPD file.
If the parameters in your IP doesn't match with the MPD parameters then this type of error occurs.
Now there are certain parameters in the MPD file which require a specification from the user side and they are mandatory.
Like in your case the parameter "OPB_Clk". Now this clock has to be specified. You can't leave this parameter unassigned.
Same is the case with the other parameter "SYS_Rst".
You need to map these or assign values whichever is applicable.
Best of luck.
--
Unlimited in my Limits.
老外给力啊 回了个信息 还是不知道怎么改啊知道是什么意思 我理解的意思是:IP核里的输入信号你没给连上 问题解决啦 呵呵 什么解决的呢?帅哥。
说说呀。
我现在也是遇到这个问题。 搞定! lions 发表于 2011-11-24 14:21 static/image/common/back.gif
搞定!
你现在还在做xinlinx fpga吗 PORT SYS_Rst = "", DIR = I, ASSIGNMENT = REQUIRE是说这个信号需要连接 你没有使用它吧
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