原创:10分频的VHDL实现,格雷码,50%占空比;欢迎拍砖.
library ieee;use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Divide_10 is
port(
clk_in : in std_logic;
clk_out : out std_logic
);
end entity;
architecture rtl of Divide_10 is
signal cnt : std_logic_vector(3 downto 0);
begin
process (clk_in)
begin
if (rising_edge(clk_in)) then
case cnt is
when "0000" =>clk_out <= '1';cnt <= "0001";
when "0001" =>clk_out <= '1';cnt <= "0011";
when "0011" =>clk_out <= '1';cnt <= "0111";
when "0111" =>clk_out <= '1';cnt <= "0110";
when "0110" =>clk_out <= '1';cnt <= "1110";
when "1110" =>clk_out <= '0';cnt <= "1100";
when "1100" =>clk_out <= '0';cnt <= "1101";
when "1101" =>clk_out <= '0';cnt <= "1001";
when "1001" =>clk_out <= '0';cnt <= "1000";
when "1000" =>clk_out <= '0';cnt <= "0000";
when others =>clk_out <= 'X';cnt <= "XXXX";
end case;
end if;
end process;
end rtl; 修改麻烦。
分频系数大时更麻烦。
所以还是计数器的好。 计数器有很大的时延，不够精确，4分，8分很容易，这个是拿来降频用的比如，48MHZ 3次十分频->48K 2次8分频->3K
你发个计数器的分频程序，给我看看示波器波形? library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clk_div2 is
generic(countmax:integer :=5);
port(CLKIN:in std_logic;
CLKOUT:BUFFER std_logic);
end;
architecture EPM570 of clk_div2 is
begin
process(CLKIN)
variable count:integer range 1 to countmax;
begin
if CLKIN'event and CLKIN='1' then
if count=count'high then
CLKOUT<=NOT CLKOUT;
count:=1;
else
count:=count+1;
end if;
end if;
end process;
end ;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clk_div is
generic(countmax:integer :=10);
port(CLKIN:in std_logic;
CLKOUT:out std_logic);
end;
architecture EPM570 of clk_div is
begin
process(CLKIN)
variable count:integer range 1 to countmax;
begin
if CLKIN'event and CLKIN='1' then
if count=count'high then
CLKOUT<='1';
count:=1;
else
count:=count+1;
CLKOUT<='0';
end if;
end if;
end process;
end ;
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