VHDL菜鸟求助
初学VHDL，写了段代码，波形仿真时出现下列警告，感觉不能综合，特向老鸟讨教，谢谢代码如下：
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY clk8 IS
PORT(
iCLK,Sft,Rst:IN STD_LOGIC;
oCLK:BUFFER STD_LOGIC;
Done:OUT STD_LOGIC
);
END clk8;
ARCHITECTURE clk8 OF clk8 IS
SIGNAL SFT_EN:BOOLEAN;
BEGIN
PROCESS(Sft,Rst,oCLK)
VARIABLE Clk_Count:INTEGER RANGE 0 TO 8;
BEGIN
IF(Rst = '1')THEN
Clk_Count := 8;
SFT_EN <= FALSE;
Done <= '1';
ELSIF(Sft = '0')THEN
SFT_EN <= TRUE;
Done <= '1';
ELSIF(oCLK'EVENT AND oCLK ='0')THEN
Clk_Count := Clk_Count -1;
IF(Clk_Count = 0)THEN
Clk_Count := 8;
SFT_EN <= FALSE;
Done <= '0';
END IF;
END IF;
END PROCESS;
oCLK <= iCLK WHEN (SFT_EN)ELSE
'0';
END clk8;
仿真警告如下
Warning: Found clock-sensitive change during active clock edge at time 80.0 ns on register "|clk8|Clk_Count"
Warning: Found clock-sensitive change during active clock edge at time 80.0 ns on register "|clk8|Clk_Count"
Warning: Found clock-sensitive change during active clock edge at time 80.0 ns on register "|clk8|Clk_Count"
Warning: Found clock-sensitive change during active clock edge at time 80.0 ns on register "|clk8|Clk_Count"
http://cache.amobbs.com/bbs_upload782111/files_38/ourdev_628598GQOAC0.jpg
(原文件名:无标题.jpg)
设计目的：在SFT的低电平触发下，从oClk输出8个上升沿到iClk信号
请菜鸟指针 有人能帮帮我吗
PS “请老鸟指正”，打成“请菜鸟指针了” - -！ 我也是菜鸟,但见过这类问题.
警告大意:不能满足时序建立要求
你的程序里IF镶套太紧凑,不能满足时序要求,改一下吧 推荐你看下RTL级电路，是不是你所需要产生的电路，然后再修改。
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