论坛首页 › FPGA › 帮我将这个程序用verilog HDL 改写出来嘛。谢谢！

liuziyi 发表于 2011-3-22 21:10:33

帮我将这个程序用verilog HDL 改写出来嘛。谢谢！

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY top IS
PORT(
      clk: IN STD_LOGIC;
      reset:IN STD_LOGIC;
      timecount:IN STD_LOGIC;
      clkout:IN STD_LOGIC;
      kmcnt2:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
      kmcnt3:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
      count1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
      count2:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

      count3:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
);
END money;
ARCHITECTURE rtl OF money IS
SINGNAL cash: STD_LOGIC_VECTOR(11 DOWNTO 0);
SINGNALprice: STD_LOGIC_VECTOR(3DOWNTO 0);
SINGNAL enable: STD_LOGIC:
BEGIN
money1：PROCESS(cash,kmcnt2)
BEGIN
IFcash>="000001000000"THEN
    price<="0100";
ELSE
    price<="0010";
END IF;
IF(kmcnt2>="0011")OR(kmcnt3>="0001")THEN
enable<=1;
ELSE
enable<=0;
END IF;
END PROCESS;
money2:PROCESS(reset,clkour,clk,enable,price,kmcnt2)
VARIABLE reg2: STD_LOGIC_VECTOR(11 DOWNTO 0);
VARIABLE clkout_cnt:INTEGER RANGE 0 TO 10;
BEGIN
IF reset=1THEN
cash<=000000000011;
ELSE IF clk'EVENT AND CLK=1 THEN
reg2:=cash;
IFreg2(3DOWNT 0)+0001>1001THEN
reg2(7DOWNT 0):=reg2(7DOWNTO 0+00000111;
IF reg2(7DOWNT4 )>1001THEN
cash<=reg2+000001100000;
ELSE
cash<=reg2;
END IF
ELSE
cash<=reg2+0001;
END IF
ELSE IFclkout=1and enable=1 THEN
IF clkout_cnt=9 THEN
   clkout_cnt:=0;
   reg2:=cash;
    IF 0000&reg2(3 DOWNTO 0)+price(3 DOWNTO 0)>00001001 THEN
      reg2(7 DOWNTO 0):=reg2(7 DOWNTO 0)+00000110+price;
       IFreg2(7 DOWNTO 4)>1001 THEN
         cash<=reg2+000001100000;
       ELSE
      cash<=reg2;
       END IF;
   ELSE
      cash<=reg2+price;
   END IF;
END IF;
END IF;
END PROCEES;
count1<=cash(3 DOWNTO 0);
count2<=cash(7DOWNTO 4);
count3<=cash(11 DOWNTO 8);
END rtl;

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