Tomas_Yung 发表于 2011-1-23 16:10:48

VHDL语言实现三相电机驱动

-- 3Phase Induction Motor Controler II --
-- INV3PA.VHD --
-- Miniprobe Pingu --

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;

entity inv3pa is
Port(
speed_clk,vector_clk,inhibit_sw,over_current : in std_logic;
port_U,port_V,port_W,port_IU,port_IV,port_IW,led : out std_logic
);
end inv3pa;

architecture RTL of inv3pa is

--6step inverter
signal hex: integer range 0 to 5;
signal cstep: integer range 0 to 4;

--vector counter
signal vector: integer range 0 to 30;
signal vecshot: std_logic_vector(1 downto 0);
signal vector_reset: std_logic;

--vectors
signal vector_x,vector_y,ivector_x,ivector_y,vector_z : std_logic;
signal UD,VD,WD : std_logic;
signal U,V,W : std_logic;

-- control
signal over_current_flag: std_logic;

begin
---------------------------------------------------------------------
-- genarate hex(6STEP INVERTER STEP VALUE) and cstep(delta STEP VALUE)
process(speed_clk)
begin
if(speed_clk'event and speed_clk='1') then
if(hex = 5 and cstep = 4) then
hex <= 0;
cstep <= 0;
else if (cstep = 4) then
cstep <= 0;
hex <= hex + 1;
else
cstep <= cstep + 1;
end if;
end if;
end if;
end process;

----------------------------------------------------------------------
-- genarate vector freerun counter
process(vector_clk,vector_reset,vector)
begin
if(vector_clk'event and vector_clk='1') then
if (vector < 30) then
vector <= vector + 1;
else
vector <= 0;
end if;
end if;
end process;

----------------------------------------------------------------------
-- reset circuit(one shot) of vector counter
-- reset at speed_clk rise edge.
process(vector_clk,speed_clk)
begin
if(vector_clk'event and vector_clk='1') then
vector_reset <= vecshot(0) and (not vecshot(1));
vecshot(1) <= vecshot(0);
vecshot(0) <= speed_clk;
end if;
end process;

----------------------------------------------------------------------
--genarate vectors
process(vector_clk,cstep, vector)
begin
if (cstep=0) then
if (vector <= 3) then vector_x <= '1'; else vector_x <= '0'; end if;
if (vector <= 24) then vector_y <= '1'; else vector_y <= '0'; end if;
if ((30-vector) >= 3) then ivector_x <= '1'; else ivector_x <= '0'; end if;
if ((30-vector) >= 24) then ivector_y <= '1'; else ivector_y <= '0'; end if;
end if;

if (cstep=1) then
if (vector <= 8) then vector_x <= '1'; else vector_x <= '0'; end if;
if (vector <= 25) then vector_y <= '1'; else vector_y <= '0'; end if;
if ((30-vector) >= 8) then ivector_x <= '1'; else ivector_x <= '0'; end if;
if ((30-vector) >= 25) then ivector_y <= '1'; else ivector_y <= '0'; end if;
end if;

if (cstep=2) then
if (vector <= 13) then vector_x <= '1'; else vector_x <= '0'; end if;
if (vector <= 26) then vector_y <= '1'; else vector_y <= '0'; end if;
if ((30-vector) >= 13) then ivector_x <= '1'; else ivector_x <= '0'; end if;
if ((30-vector) >= 26) then ivector_y <= '1'; else ivector_y <= '0'; end if;
end if;

if (cstep=3) then
if (vector <= 17) then vector_x <= '1'; else vector_x <= '0'; end if;
if (vector <= 25) then vector_y <= '1'; else vector_y <= '0'; end if;
if ((30-vector) >= 17) then ivector_x <= '1'; else ivector_x <= '0'; end if;
if ((30-vector) >= 25) then ivector_y <= '1'; else ivector_y <= '0'; end if;
end if;

if (cstep=4) then
if (vector <= 21) then vector_x <= '1'; else vector_x <= '0'; end if;
if (vector <= 24) then vector_y <= '1'; else vector_y <= '0'; end if;
if ((30-vector) >= 21) then ivector_x <= '1'; else ivector_x <= '0'; end if;
if ((30-vector) >= 24) then ivector_y <= '1'; else ivector_y <= '0'; end if;
end if;
end process;


----------------------------------------------------------------------
--output vector for 6step inverter
process(vector_clk,vector, hex, vector_x, vector_y, ivector_y, ivector_x)
begin
if (vector <= 26) then vector_z <= '1'; else vector_z <= '0';
end if;

if (hex=0) then
U <= vector_x; V <= '0'; W <= vector_y; else
if (hex=1) then
U <= vector_z; V <= ivector_y; W <= ivector_x; else
if (hex=2) then
U <= vector_y; V <= vector_x; W <= '0'; else
if (hex=3) then
U <= ivector_x; V <= vector_z; W <= ivector_y; else
if (hex=4) then
U <= '0'; V <= vector_y; W <= vector_x;
else
U <= ivector_y; V <= ivector_x; W <= vector_z;
end if;
end if;
end if;
end if;
end if;
end process;

-----------------------------------------------------------------------------------

-- Dead Time Genarate of upper and lower side.
-- and inhibit_sw. ,over current control.

-- Dead Time Genarate
process(vector_clk)
begin
if(vector_clk'event and vector_clk='1') then
UD <= U;
VD <= V;
WD <= W;
end if;
end process;

-- over current lach
-- reset lach at only power on again.
process(over_current)
begin
if over_current='1' then
over_current_flag <='1';
led <= '1';
end if;
end process;

-- output control
port_U <= (U and UD) and inhibit_sw and not over_current_flag;
port_IU <= (not(U or UD)) and inhibit_sw and not over_current_flag;

port_V <= (V and VD) and inhibit_sw and not over_current_flag;
port_IV <= (not(V or VD)) and inhibit_sw and not over_current_flag;

port_W <= (W and WD) and inhibit_sw and not over_current_flag;
port_IW <= (not(W or WD)) and inhibit_sw and not over_current_flag;

-----------------------------------------------------------------------------------
end RTL;

rlogin 发表于 2011-1-24 06:36:14

就看到一堆代码,没看懂

laokongzhuang 发表于 2011-1-24 21:17:45

如果能有些注释就完美了!
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