Modelsim仿真出错，求助~！
我用quartus10.0，仿真用modelsim 6.5e，VHDL程序。modelsim编译结果如下：# vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L cycloneii -L rtl_work -L work -voptargs="+acc" clk_div_vhd_tst
# vsim -L altera -L lpm -L sgate -L altera_mf -L cycloneii -L rtl_work -L work -voptargs=\"+acc\" -t 1ps clk_div_vhd_tst
# ** Error: Failure to obtain a VHDL simulation license.
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./LED_run_msim_rtl_vhdl.do PAUSED at line 12
本人是按网上教程破_解的，为什么还说 Failure to obtain a VHDL simulation license.
求大虾帮助~！
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