请教FPGA读写USB 68013
module fifo_usb(clk,start,data1,q,data2,ifclk,fifoadr,slcs,pktend,sloe,slrd,slwr);
input clk;
input start;
input data1;
inout q;
output data2;
output ifclk;
output fifoadr;
output slcs,pktend,sloe,slrd,slwr;
reg state,next_state;
reg strx,stry;
reg flag;
reg rst;
reg cnt2=0;
reg data_test;
reg count;
reg ccnt,ccnt2;
reg f0,f1,f2,f3,f4,f5,f6,f7;
assign sda=1'bz;
assign sda1=1'bz;
assign sda2=1'bz;
assign sda3=1'bz;
assign sda4=1'bz;
assign scl=1'bz;
assign scl1=1'bz;
assign scl2=1'bz;
assign scl3=1'bz;
assign scl4=1'bz;
parameter state0=3'b000,state1=3'b001,state2=3'b011,state3=3'b010,
state4=3'b110,state5=3'b111,state6=3'b101,state7=3'b100;
always@(posedge clk)
begin
cnt2<=cnt2+1;
if(cnt2>=100)
begin cnt2<=105; rst<=1;end
else if(cnt2>=0&&cnt2<=90)
rst<=0;
else rst<=1;
end
assign slcs=0;
assign pktend=1;
assign q=(flag)?data_reg:16'bz;
pll_1 mypll_1(.CLK(clk),.CLKOP(ifclk));
always@(posedge ifclk or negedge rst)
begin
if(!rst)
begin
strx<=0;
stry<=0;
end
else
begin
strx<=start;
stry<=strx;
end
end
always@(negedge ifclk or negedge rst)
begin
if(!rst)
state<=state0;
else
state<=next_state;
end
always@(state or uempty or ufull or stry or strx or count)
begin
case(state)
state0: begin
count<=0;
if(!stry&&strx==1)
next_state<=state1;
else
next_state<=state0;
end
state1: begin
if(uempty==1)
next_state<=state2;
else
next_state<=state1;
end
state2: begin
next_state<=state3;
end
state3: begin
if(uempty==1)
next_state<=state2;
else if(data_test==16'hc050)
next_state<=state4;
else
next_state<=state0;
end
state4: begin
if(!stry&&strx==1)
next_state<=state5;
else
next_state<=state4;
end
state5: begin
if(ufull==1)
next_state<=state6;
else
next_state<=state5;
end
state6: begin
next_state<=state7;
end
state7: begin
if(ufull==1)
next_state<=state6;
else if(count<10)
begin
next_state<=state5;
count<=count+1;
end
else
begin
next_state<=state0;
count<=0;
end
end
default: next_state<=state0;
endcase
end
always@(state)
begin
case(state)
state0: begin
slrd<=1;
sloe<=1;
slwr<=1;
fifoadr<=2'b00;
flag<=0;
f0<=1;f1<=0;f2<=0;f3<=0;f4<=0;f5<=0;f6<=0;f7<=0;
end
state1: begin
slrd<=1;
sloe<=1;
slwr<=1;
fifoadr<=2'b00;
f0<=0;f1<=1;f2<=0;f3<=0;f4<=0;f5<=0;f6<=0;f7<=0;
end
state2: begin
slrd<=1;
sloe<=0;
slwr<=1;
flag<=0;
f0<=0;f1<=0;f2<=1;f3<=0;f4<=0;f5<=0;f6<=0;f7<=0;
end
state3: begin
slrd<=0;
sloe<=0;
slwr<=1;
data2<=q;
data_test<=16'hc050;
f0<=0;f1<=0;f2<=0;f3<=1;f4<=0;f5<=0;f6<=0;f7<=0;
end
state4: begin
slrd<=1;
sloe<=1;
slwr<=1;
fifoadr<=2'b00;
//flag<=1;
f0<=0;f1<=0;f2<=0;f3<=0;f4<=1;f5<=0;f6<=0;f7<=0;
end
state5: begin
fifoadr<=2'b10;
slrd<=1;
sloe<=1;
slwr<=1;
flag<=1;
f0<=0;f1<=0;f2<=0;f3<=0;f4<=0;f5<=1;f6<=0;f7<=0;
end
state6: begin
slrd<=1;
sloe<=1;
slwr<=1;
flag<=1;
f0<=0;f1<=0;f2<=0;f3<=0;f4<=0;f5<=0;f6<=1;f7<=0;
end
state7: begin
slrd<=1;
sloe<=1;
slwr<=0;
data_reg<={ccnt,ccnt2};//16'haaaa;//data1;
flag<=1;
f0<=0;f1<=0;f2<=0;f3<=0;f4<=0;f5<=0;f6<=0;f7<=1;
end
default: begin
slrd<=1;
sloe<=1;
slwr<=1;
fifoadr<=2'b00;
end
endcase
end
always@(posedge ifclk or negedge rst)
begin
if(!rst)
begin ccnt<=0; ccnt2<=0; end
else
if(slwr==0)
begin ccnt<=ccnt+1; ccnt2<=ccnt2+1; end
else
begin ccnt<=ccnt; ccnt2<=ccnt2; end
end
//assign t1=ufull;
//assign t2=uempty;
//assign t3=f5;
//assign t4=f6;
endmodule 什么问题？
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