贡献一个verlog实现的4，7线性分组码编解码代码
/**编码器
* Licence CC
* Date:2010-12-21
* Auther:YaoH
*
* G Matrix
* 1101000
* 0110100
* 1110010
* 1010001
*
*/
module LBC4_7_ENC (DIN,COUT,CLK,RST);
//DIN数据入
//COUT编码后代码输出
//
//
input DIN;
input CLK;
input RST;
output COUT;
reg ob;
reg ib;
always@(posedge CLK)
begin
if(RST==1'b1)
begin
ib=DIN;
case(ib)
4'b0000: ob<=7'b0000000;
4'b1000: ob<=7'b1101000;
4'b0100: ob<=7'b0110100;
4'b1100: ob<=7'b1011100;
4'b0010: ob<=7'b1110010;
4'b1010: ob<=7'b0011010;
4'b0110: ob<=7'b1000110;
4'b1110: ob<=7'b0101110;
4'b0001: ob<=7'b1010001;
4'b1001: ob<=7'b0111001;
4'b0101: ob<=7'b1100101;
4'b1101: ob<=7'b0001101;
4'b0011: ob<=7'b0100011;
4'b1011: ob<=7'b1001011;
4'b0111: ob<=7'b0010111;
4'b1111: ob<=7'b1111111;
endcase
end
else
begin
ob<=7'b0000000;
end
end
assign COUT=ob;
endmodule
/*
*解码器
* Licence CC
* Date:2010-12-21
* Auther:YaoH China
*
* H Matrix
* 1001011
* 0101110
* 0010111
*
*
*/
module LBC4_7_DEC(CIN,DOUT,CLK,RST);
//CIN编码输入
//DOUT数据输出
input CIN;
input CLK;
input RST;
output DOUT;
reg ib;
reg ob;
reg s;
reg e;
always @(posedge CLK)
begin
ib=CIN;
//get S
s=ib+ib+ib+ib;
s=ib+ib+ib+ib;
s=ib+ib+ib+ib;
//get E
case(s)
3'b000:e=7'b0000000;
3'b100:e=7'b1000000;
3'b010:e=7'b0100000;
3'b001:e=7'b0010000;
3'b110:e=7'b0001000;
3'b011:e=7'b0000100;
3'b111:e=7'b0000010;
3'b101:e=7'b0000001;
endcase
ib=ib+e;
ob=ib;
end
assign DOUT=ob;
endmodule thx mark
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