写了一个pci接口，大家帮忙看看！
LIBRARY ieee;USE ieee.std_logic_1164.All;
USE ieee.std_logic_unsigned.ALL;
ENTITY cpci IS
PORT(clk,rst,frame,irdy:IN STD_LOGIC;
ad_high : IN STD_LOGIC_VECTOR(31 downto 24);
ad_low : IN STD_LOGIC_VECTOR(12 downto 0);
c_be : IN STD_LOGIC_VECTOR(3 downto 0);
trdy,devsel:OUT STD_LOGIC;
cs, r_w :OUT STD_LOGIC;
addr: OUT STD_LOGIC_VECTOR(12 downto 0)
);
END cpci;
ARCHITECTURE behave OF cpci IS
SIGNAL addr_map : STD_LOGIC_VECTOR(12 downto 0);
SIGNAL read,write,cs_map:STD_LOGIC;
TYPE state_type IS(s0,s1,s2,s3,s4,s5);
SIGNAL state: state_type;
BEGIN
Identify: PROCESS(clk)
BEGIN
IF rising_edge(clk)THEN
IF c_be=X"6"AND ad_high=X"50"AND state=s1
THEN read<= '0';
write<= '1';
cs_map<='0';
ELSIF c_be=X"7"AND ad_high= X"50"
AND state=s1 THEN
read<= '1';
write<= '0';
cs_map<='0';
ELSIF state=s0 THEN
read <= '1';
write <= '1';
cs_map <='1';
END IF;
END IF;
END PROCESS;
Addr_count:PROCESS (clk)
BEGIN
IF falling_edge(clk)THEN
IF state=s1 THEN addr_map<= ad-low;
ELSIF state=s3 THEN addr_map<= addr_map+'1';
END IF;
END IF;
END PROCESS;
addr<= addr_map WHEN state=s3 OR state=s4
ELSE "ZZZZZZZZZZZZZ" ;
trdy <='0' WHEN state=s3 OR state=s4 OR state=s5
ELSE '1';
devsel <='0' WHEN state=s3 OR state=s4 OR state=s5
ELSE '1';
cs <='0' WHEN state=s3 OR state=s4 ELSE '1';
r_w<=NOT clk WHEN write='0'AND (state=s3 OR state=s4)
ELSE '1';
state_change:PROCESS(clk,rst)
BEGIN
IF rst='0'THEN state<=s0;
ELSIF falling-edge(clk) THEN CASE state IS WHENs0 = >
IF frame='1'AND irdy='1'THEN state < = s0;
ELSIF frame='0' AND irdy= '1' THEN state < = s1;
END IF;
WHEN s1 = >
IF cs_map='1'OR (read='1'AND write ='1')
THEN state < = s0;
ELSIF irdy='1'AND read='0' THEN state < =s2;
ELSIF frame='0'AND irdy='0'AND write='0'
THEN state < = s3;
ELSIF frame='1'AND irdy='0'AND write='0'
THEN state < = s4;
END IF;
WHEN s2 = >
IF frame='1'AND irdy='1'THEN state < = s0;
ELSIF frame='0'AND irdy='0'AND read='0'
THEN state < = s3;
ELSIF frame='1'AND irdy='0'AND read='0'
THEN state < = s4;
END IF;
WHEN s3 = >
IF frame='1'AND irdy='1'THEN state < = s0;
ELSIF frame='0' AND irdy= '1' THEN state < = s5;
ELSIF frame='1'AND irdy='0' THEN state < =s4;
ELSIF frame='0' AND irdy= '1' THEN state < = s3;
END IF;
WHEN s4 = >
ELSIF frame='1'AND irdy='0'THEN state < = s4;
END IF;
WHEN s5 = >
IF frame='1'AND irdy='1'THEN state < = s0;
ELSIF frame='0' AND irdy= '0'THEN state < = s3;
ELSIF frame='1'AND irdy='0' THEN state < =s4;
ELSE state < = s5;
END IF;
WHEN OTHERS = > state < = s0;
END CASE;
END IF;
END PROCESS state_change;
END behave
折腾一晚上编译有个错误，大家帮忙瞧瞧！
等弄好再上传......
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