大家有谁用verilog写过ADC0809的代码啊，AD0809的时钟怎么处理啊，最好有代码给小弟膜拜
我的24M晶振，用多少分频可以得到AD0809说需要的时钟了，一般是500k吧。还有这是我的verilog代码，欢迎大家指教啊。我测试好像不对哦//==========ADC0809 -m采集数据 状态机============================
parameter st0 = 3'b000;
parameter st1 = 3'b001;
parameter st2 = 3'b010;
parameter st3 = 3'b011;
parameter st4 = 3'b100;
parameter st5 = 3'b101;
reg state,next_state;
regoe,start,lock;
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)begin
state<=0;
end
else begin
state<=next_state;
end
end
reg cnt;//定义一个2位的计数器，如果我用的25M的晶振。那么时钟周期就是40ns。计数4次就至少有100ns的高电平啦
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)begin
cnt<=2'b0;
end
else begin
cnt<=cnt+1'b1;
end
end
always@(state or eoc)
begin
case(state)
st0:begin
start<=0;
oe<=0;
lock<=0;
next_state<=st1;
end
st1:begin
start<=1;
oe<=0;
lock<=0;
if(cnt==2'b11)begin//分频计数使start 维持至少100ns，仿真结果是120ns
next_state<=st2;
end
else begin
next_state<=st1;
end
end
st2:begin
start<=0;
oe<=0;
lock<=0;
next_state<=st3;
end
st3:begin
start<=0;
oe<=0;
lock<=0;
if(eoc==0)
next_state<=st3;
else
next_state<=st4;
end
st4:begin
start<=0;
oe<=1;
lock<=1;
next_state<=st5;
end
st5:begin
start<=0;
oe<=1;
lock<=1;
next_state<=st0;
end
default:begin
start<=0;
oe<=0;
lock<=0;
next_state<=st0;
end
endcase
end
regm1;
always @(posedge lock)
begin
m1<=m;
end
reg cba_r;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
cba_r<=0;
else
cba_r<=3'b011;
end
assign cba=cba_r;
//======================================================== 求 高手给一个用AD0809 实现Ad采样~使用VHDL语言的啊~~ 是fpga还是cpld？
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