请大家帮看看这段Verilog的问题
请各位高手帮看下最后那个小脉冲怎么出来的？如何去掉？谢谢http://cache.amobbs.com/bbs_upload782111/files_35/ourdev_601587KND81V.JPG
(原文件名:12月1日总是图.JPG)
程序如下：
module vga(dclk,hs,vs,pspclk,pspclk1);
input dclk;
output hs,vs,pspclk,pspclk1;
reg hs,vs,pspclk,pspclk1;
reg count_v,count_h;
reg flag,i,j;
always@(posedge pspclk1)begin
if(count_h==16) count_h<=0;
else
count_h<=count_h+1;
end
always@(posedge pspclk1)begin
if(count_v==10) count_v<=0;
else if(count_h==16) count_v<=count_v+1;
end
always@(posedge pspclk1)
begin
if(count_h==0) hs<=1;
if(count_h==3) vs<=0;
if(count_h==2) hs<=0;
if(count_v==0&&count_h<3)vs<=1;
end
always@(posedge dclk)
begin
if(j==1)
begin
pspclk1<=~pspclk1;
j<=0;
end
else
j<=j+1;
end
always@(pspclk1)
begin
if(count_h<4)
pspclk<=0;
else
pspclk<=pspclk1;
end
endmodule 就是pspclk2.7us附近那个小的百思不得解 大家看看 ，欢迎拍砖 同步设计，消除毛刺 always@(pspclk1)
begin
if(count_h<4)
pspclk<=0;
else
pspclk<=pspclk1;
end
这个改成
assign pspclk=(count_h<4) ? 0 : pspclk1;
试试 回复【2楼】suipeng70
-----------------------------------------------------------------------
感谢回复能具体说一点吗？不是很理解 如果是组合电路引起的毛刺的话，在输出加一个d触发器就好了
页:
[1]