MSP430奇怪的问题
今天我做一个430小实验,程序是在TI下载的,我改了一些参数,发现一个奇怪的问题:MCLK输出的频率不正常。程序如下:
#include"msp430x54x.h"
void main(void)
{
WDTCTL = WDTPW+WDTHOLD; // Stop WDT
P1DIR |= BIT0; // P1.0 output
P11DIR |= 0x07; // ACLK, MCLK, SMCLK set out to pins
P11SEL |= 0x07; // P11.0,1,2 for debugging purposes.
UCSCTL3 |= SELREF_2; // Set DCO FLL reference = REFO
UCSCTL4 |= SELA_2; // Set ACLK = REFO
__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_5; // Select DCO range 24MHz operation
UCSCTL2 = FLLD__2 + 99; // Set DCO Multiplier for 12MHz
// (N + 1) * FLLRef = Fdco
// (374 + 1) * 32768 = 12MHz
// Set FLL Div = fDCOCLK/2
__bic_SR_register(SCG0); // Enable the FLL control loop
// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 12 MHz / 32,768 Hz = 375000 = MCLK cycles for DCO to settle
__delay_cycles(375000);
// Loop until XT1,XT2 & DCO fault flag is cleared
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG); // Test oscillator fault flag
while(1)
{
P1OUT ^= BIT0; // Toggle P1.0
__delay_cycles(600000); // Delay
}
}
这句UCSCTL2 = FLLD__2 + 99;,我侧输出频率是3.2MHz,是对的,改成UCSCTL2 = FLLD__1 + 99;和UCSCTL2 = FLLD__16 + 99;时,输出频率就分别是4M多和2.3M多,改成UCSCTL2 = FLLD__4 + 99;和UCSCTL2 = FLLD__8 + 99;时,是对的3.2M,为什么FLLD__1和FLLD__16就不对了呢?按公式算结果都是一个3.2M啊,请问这是怎么回事啊,请求大家帮助,指点一下,多谢啦,各位好心人! 没人回答,自己先顶一个。 http://cache.amobbs.com/bbs_upload782111/files_34/ourdev_599828LE4OEQ.jpg
(原文件名:pll.jpg)
自己对着图计算吧,建议你好好读读手册,先理解怎么计算 回复【2楼】again
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请问,我看了用户手册上有公式:
fDCOCLK = D × (N + 1) × (fFLLREFCLK ÷ n)
fDCOCLKDIV = (N + 1) × (fFLLREFCLK ÷ n)
MCLK默认的输出频率是fDCOCLKDIV,所以与D无关,我在程序里面这条语句UCSCTL2 = FLLD__2 + 99;中的FLL__D改了,其他变量都没有改变,结果应该是不变的啊,请问能具体讲一下吗?谢谢了!
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