package 编写和调用问题
我刚学VHDL语言,编写一个package包,然后调用,可是好多错误,请大侠指点;library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
package dp16 is
function add( a :std_logic;
b :std_logic)
return std_logic;
enddp16;
package body dp16 is
function add(a:std_logic;
b:std_logic)
return std_logic is
variable tmp:std_logic;
begin
tmp := a + b;
return tmp;
end add;
enddp16;
这是我写的package,下面为顶层程序:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.dp16.all;
entity adder is
port(en:in std_logic;
a:in std_logic;
b:in std_logic;
cout:out std_logic
);
end adder;
architecture behav of adder is
begin
process(en)
begin
if en='1' then cout<=add(a,b);
--elsif en='0' thencout<='0';
else null;
end if;
end process;
end behav;
提示下面的错误
Error (10327): VHDL error at dp16.vhd(17): can't determine definition of operator ""+"" -- found 0 possible definitions 哪位大侠可以指点一下写程序包的具体步骤和方法啊?还有包文件存储的后缀名是VHD吗?怎么加进去
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