第一次发帖----高叫射Xilinx杯 山东B题 基于FPGA的数字存储示波器 源代码
今年暑假做的，嵌了MicroBlaze软核，全部的代码，Verilog和C因为以前仿过魏昆同学，所以轻松拿省一了、、、、、、、、
感谢万能的坛子。
/////////////////////////////////////////////////////////////////////By Ljt
////////////////////////////////////top moudle main_ctrl.v
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: SDU
// Engineer: Ljt
// Create Date: 20:08:59 08/28/2010
// Module Name: top_moudule
// Project Name: MPU_VGA
//////////////////////////////////////////////////////////////////////////////////
module vga_top_moudule(
clk,
//VGA的IO
h_sync,v_sync,red,green,blue,
//MicroBlaze核用IO
fpga_0_Micron_RAM_Mem_A_pin,fpga_0_Micron_RAM_Mem_CEN_pin,,fpga_0_Micron_RAM_Mem_OEN_pin,
fpga_0_Micron_RAM_Mem_WEN_pin,fpga_0_Micron_RAM_Mem_BEN_pin,fpga_0_Micron_RAM_Mem_DQ_pin,
fpga_0_rst_1_sys_rst_pin,
//外设
fpga_0_LEDs_8Bit_GPIO_IO_O_pin,
fpga_0_Push_Buttons_4Bit_GPIO_IO_I_pin,
fpga_0_Switches_8Bit_GPIO_IO_I_pin,
fpga_0_RS232_PORT_RX_pin,
fpga_0_RS232_PORT_TX_pin,
//键盘
ps2k_clk,ps2k_data,
//AD
max1242_sclk,max1241_cs,max1241_data,sam_clk_out,ad_data,
//EEP//继电器
gpio_5,JiDaQ,
//数字输入，数字输出
digt_in,digt_a,digt_b
);
input clk;//50MHz
//VGA
output h_sync,v_sync;
output red;
output green;
output blue;
//数字输出
output digt_a;
output reg digt_b;
//AD
output max1242_sclk,max1241_cs;
input max1241_data;
//EEP
inout gpio_5;
//键盘
input ps2k_clk;
input ps2k_data;
//IP外设
output fpga_0_LEDs_8Bit_GPIO_IO_O_pin;
input fpga_0_Switches_8Bit_GPIO_IO_I_pin;
input fpga_0_Push_Buttons_4Bit_GPIO_IO_I_pin;
input fpga_0_RS232_PORT_RX_pin;
output fpga_0_RS232_PORT_TX_pin;
output JiDaQ;
input digt_in;
//CPU的RAM引脚
output fpga_0_Micron_RAM_Mem_A_pin;
output fpga_0_Micron_RAM_Mem_CEN_pin;
output fpga_0_Micron_RAM_Mem_OEN_pin;
output fpga_0_Micron_RAM_Mem_WEN_pin;
output fpga_0_Micron_RAM_Mem_BEN_pin;
inout fpga_0_Micron_RAM_Mem_DQ_pin;
input fpga_0_rst_1_sys_rst_pin;
//模块之间的互联信号
wire clkb;
wire addrb;
wire doutb;
wire addra;
wire dina;
wire mainclk;
wire clk100M;
wire wea=1;
wire keyclr=1;
wire xps_gpio_2_GPIO_IO_I_pin;
wire xps_gpio_3_GPIO_IO_I_pin;
wire rst_n=fpga_0_rst_1_sys_rst_pin;
wire ps2_byte;
wire ps2_state;
wire gpio4;
wire iobuf;
wire b_doutb;
wire markline;
//寄存器变量
//连续性赋值
assign clka=clk100M;
assign xps_gpio_2_GPIO_IO_I_pin=ps2_state;
assign xps_gpio_2_GPIO_IO_I_pin=ps2_byte;
assign xps_gpio_2_GPIO_IO_I_pin=0;
assign iobuf=gpio4;//6位
assign markline=gpio4;
//assign xps_gpio_3_GPIO_IO_I_pin=max1241_data;//接到了gpio3上
assign max1241_cs=gpio4;
assign max1242_sclk=gpio4;
wire sam_start,sam_done;
wire ad_addra;
//AD IO
output sam_clk_out;
input ad_data;
wire sam_clk;
wire ad_doutb;//MCU,in
wire ad_addrb;//MCU use,o
wire clkdivid;//MCU ,o
assign ad_addrb=gpio4;
assign sam_start=gpio4;
assign clkdivid=gpio4;
assignxps_gpio_3_GPIO_IO_I_pin=ad_doutb;
assignxps_gpio_3_GPIO_IO_I_pin=ad_addra;
wire trig_1sa;//CPU给出，置1单次触发状态
wire trig_now;//Comp模块给出
assign trig_1sa=gpio4;//6位
////////////////////////////////////////////////////例化各个模块
wire addrb_b;
wire b_wave_clk;
vga vgadrv (
.mainclk(mainclk),
.h_sync(h_sync),
.v_sync(v_sync),
.red(red),
.green(green),
.blue(blue),
.clkb(clkb),
.addrb(addrb),
.doutb(doutb),
.b_doutb(b_doutb),
.markline(markline),
.addrb_b(addrb_b),
.clk(b_wave_clk)
);
reg r_addra; reg b_addra;
reg r_dina; reg b_dina;
b_GRam_wave b_GRam_wave (
.clka(clka),
.wea(wea), // Bus
.addra(b_addra), // Bus
.dina(b_dina), // Bus
.clkb(b_wave_clk),
.addrb(addrb_b), // Bus
.doutb(b_doutb)); // Bus
GRam GRam (
.clka(clka),
.wea(wea),
.addra(r_addra),
.dina(r_dina),
.clkb(clkb),
.addrb(addrb),
.doutb(doutb)
);
always@(posedge clk100M)
begin
if(addra) begin b_addra<=addra; b_dina<=dina; end
else begin r_addra<=addra; r_dina<=dina; end
end
wire gpio6;
reg per_reg;
MicroBlaze MicroBlaze (
.fpga_0_LEDs_8Bit_GPIO_IO_O_pin(fpga_0_LEDs_8Bit_GPIO_IO_O_pin),
.fpga_0_Push_Buttons_4Bit_GPIO_IO_I_pin(fpga_0_Push_Buttons_4Bit_GPIO_IO_I_pin),
.fpga_0_Switches_8Bit_GPIO_IO_I_pin(fpga_0_Switches_8Bit_GPIO_IO_I_pin),
.fpga_0_RS232_PORT_RX_pin(fpga_0_RS232_PORT_RX_pin),
.fpga_0_RS232_PORT_TX_pin(fpga_0_RS232_PORT_TX_pin),
.fpga_0_Micron_RAM_Mem_A_pin(fpga_0_Micron_RAM_Mem_A_pin),
.fpga_0_Micron_RAM_Mem_CEN_pin(fpga_0_Micron_RAM_Mem_CEN_pin),
.fpga_0_Micron_RAM_Mem_OEN_pin(fpga_0_Micron_RAM_Mem_OEN_pin),
.fpga_0_Micron_RAM_Mem_WEN_pin(fpga_0_Micron_RAM_Mem_WEN_pin),
.fpga_0_Micron_RAM_Mem_BEN_pin(fpga_0_Micron_RAM_Mem_BEN_pin),
.fpga_0_Micron_RAM_Mem_DQ_pin(fpga_0_Micron_RAM_Mem_DQ_pin),
.fpga_0_clk_1_sys_clk_pin(clk100M),
.fpga_0_rst_1_sys_rst_pin(fpga_0_rst_1_sys_rst_pin),
.xps_gpio_0_GPIO_IO_O_pin(dina),
.xps_gpio_1_GPIO_IO_O_pin(addra),
.xps_gpio_2_GPIO_IO_I_pin(xps_gpio_2_GPIO_IO_I_pin),
.xps_gpio_3_GPIO_IO_I_pin(xps_gpio_3_GPIO_IO_I_pin),
.xps_gpio_4_GPIO_IO_O_pin(gpio4),
.xps_gpio_5_GPIO_IO(gpio_5),
.JiDaQ_GPIO_IO_O_pin(JiDaQ),
.xps_gpio_digt_ctrl_GPIO_IO_O_pin(gpio6),
.xps_gpio_freq_GPIO_IO_I_pin(per_reg)
);
MCU_OutputCantain McuIObuf (
.ioblock(iobuf),
.mainclk(mainclk)
);
ClockManger DPLL (
.CLKIN_IN(clk),
.CLKIN_IBUFG_OUT(CLK0_OUT),
.CLK0_OUT(mainclk),
.CLK2X_OUT(clk100M)
);
ps2scan ps2scan( .clk(mainclk), //按键扫描模块
.rst_n(rst_n),
.ps2k_clk(ps2k_clk),
.ps2k_data(ps2k_data),
.ps2_byte(ps2_byte),
.ps2_state(ps2_state)
);
wire ad_data_10bit;
reg ad_data_reg;
always@(posedge sam_clk)
ad_data_reg<=ad_data_10bit;
assign ad_data_10bit=ad_data;
assign ad_data_10bit=digt_in;
AD_Cache AD_Cache (
.clka(sam_clk),
.wea(wea), // 1
.addra(ad_addra), //
.dina(ad_data_reg), //ad输入
.clkb(clk100M),
.addrb(ad_addrb), // Bus
.doutb(ad_doutb)); // Bus
AD_Sample_Ctrl Sample_Ctrl (
.clk100M(clk100M),
.sam_startin(sam_start),
.clkdivid(clkdivid),
.sam_clk(sam_clk),
.ad_addra(ad_addra),
.trig_now(trig_now),
.sam_clk_out(sam_clk_out)
);
Comp_trig Comp_trig (
.sam_clk(sam_clk),
.clk100M(clk100M),
.trig_1sa(trig_1sa),
.trig_now(trig_now),
.ad_data_reg(ad_data_reg)
);
reg digt_a0;
reg per_cnt;
reg digt_freq;
reg digt_a;
reg data_cnt;
reg c_data_cnt;
always@(posedge clk100M)//频率设置
begin
case(gpio6)
4'h1:data_cnt=16'd500; //100K
4'h2:data_cnt=16'd250;//200K
4'h3:data_cnt=16'd167;//300K 500/3
4'h4:data_cnt=16'd125; //400K 500/4
4'h5:data_cnt=16'd100; //500K
4'h6:data_cnt=16'd83; //600K
4'h7:data_cnt=16'd71; //700K
4'h8:data_cnt=16'd63; //800K
4'h9:data_cnt=16'd56; //900K
4'h10:data_cnt=16'd50; //1M
default:data_cnt=16'd100; //100K
endcase
if(c_data_cnt==data_cnt)
begin
c_data_cnt<=1;
digt_freq<=~digt_freq;
end
else
c_data_cnt<=c_data_cnt+1;
end
always@(posedge clk100M)//频率设置
begin
if(gpio6==0)
digt_a<=ad_data>480;
else
digt_a<=digt_freq;
end
always@(posedge clk100M)
begin
digt_a0<=digt_a;
end
always@(posedge clk100M)
begin
if(digt_a==1&digt_a0==0)//检测到digta上升
begin
per_reg<=per_cnt;//记录周期
per_cnt<=0;
end
else
per_cnt<=per_cnt+1;
end
always@(posedge clk100M)
begin
if(per_cnt>per_reg/8&&per_cnt<per_reg/8+per_reg/8+per_reg/8)//在1/8到3/8周期之间，b为1
digt_b<=1;
else
digt_b<=0;
end
endmodule
//////////////////////////////vga.v
//功能：将GRAM数据送至VGA，32bit*10 X 240.bit置位为红色。
module vga(mainclk,h_sync,v_sync,red,green,blue,clkb,addrb,doutb,b_doutb,markline,addrb_b,clk);
input mainclk; //主时钟，50MHz
input markline;
// base vga io define
output h_sync,v_sync;
output red;
output green;
output blue;
// DualPORT Ram
output clkb;
output addrb;
input doutb;
input b_doutb;
//reg define
reg h_sync,v_sync;
reg red;
reg green;
reg blue;
reg clkb;
reg addrb;
reg h_conter;
reg v_conter;
wire h_max=(h_conter==794);
wire v_max=(v_conter==528);
////////////////////////////////////////////////////
reg maindivd;//对50M时钟进行分频，产生25MHZ的像素时钟
output reg clk;
always@(posedge mainclk)
if(maindivd==1)
begin
maindivd<=0;
clk<=1;
end
else
begin
maindivd<=maindivd+1;clk<=0;
end
always@(posedge clk)
if(h_max)
h_conter<=0;
else
h_conter<=h_conter+1;
always@(posedge clk) //every clk do v_conter+1
if(v_max)
v_conter<=0;
else if(h_max)
v_conter<=v_conter+1;
always@(posedge clk)
begin
h_sync<= ( h_conter<=700);//行同步脉冲
v_sync<= ( v_conter<=526) ;//场同步
end
reg clk_haf;//水平分辨率减半
reg ram_bit_cnt;
reg h_ram_cnt;
always@(posedge clk)
begin
if(h_conter==51)
clk_haf<=0;
else
clk_haf<=~clk_haf;
end
reg vlflag;//竖直分辨率减半
reg h_lg;
always@(posedge clk) //32bit操作的位计数器
begin
if(h_conter==52&clk_haf)
ram_bit_cnt<=0;
else if(ram_bit_cnt==31&clk_haf)///////1
ram_bit_cnt<=0;
else if(h_conter>52&h_conter<692&clk_haf)
ram_bit_cnt<=ram_bit_cnt+1;
end
always@(posedge clk) //行标志，用来隔行重复一行
begin
if(h_conter==52)
vlflag<=~vlflag;
end
always@(posedge clk)//读取RAM控制
begin
if(v_conter==32&&(h_conter==53))//场开始时候清零
begin
addrb<=1;
end
else if(vlflag==1&&h_conter==50)
addrb<=addrb-10; //隔行重复一行
else if(ram_bit_cnt==30&&h_conter>52&clk_haf)
addrb<=addrb+1;
if(ram_bit_cnt==31)
clkb<=1;
else
clkb<=0;
end
output reg addrb_b;
reg x2_doutb;reg x2_doutb0;reg x2_doutb1;
reg gx2_doutb;reg gx2_doutb0;reg gx2_doutb1;
reg rx2_doutb;reg rx2_doutb0;reg rx2_doutb1;
reg avg_rx2_doutb;
always@(posedge clk)//读取b_RAM控制
begin
addrb_b<=(h_conter-48)/2;
x2_doutb<=b_doutb+15;
x2_doutb0<=x2_doutb;
x2_doutb1<=x2_doutb0;
rx2_doutb<=b_doutb+15;
rx2_doutb0<=rx2_doutb;
rx2_doutb1<=rx2_doutb0;
gx2_doutb<=b_doutb+15;
gx2_doutb0<=gx2_doutb;
gx2_doutb1<=gx2_doutb0;
if(h_conter==0)
avg_rx2_doutb<=(rx2_doutb0+rx2_doutb)/2;
else
avg_rx2_doutb<=rx2_doutb;
end
reg blue_flag,red_flag,gren_flag;
always@(posedge clk)//在这里将线加粗
begin
blue_flag<=(x2_doutb>=v_conter-1&x2_doutb0<=v_conter)|(x2_doutb<=v_conter&x2_doutb0>=v_conter-1);
gren_flag<=(gx2_doutb>=v_conter-1&gx2_doutb0<=v_conter)|(gx2_doutb<=v_conter&gx2_doutb0>=v_conter-1);
red_flag<=(rx2_doutb>=v_conter-1&avg_rx2_doutb<=v_conter)|(rx2_doutb<=v_conter&avg_rx2_doutb>=v_conter-1);
end
always@(posedge clk)
if( (h_conter<55)|(h_conter>690)|(v_conter<30)|(v_conter>516))//分辨率640X480. 从53-692：640 * 30-519：480
begin
red<=0;
green<=0;
blue<=0;
end
else if(h_conter%2==0&&v_conter==markline+31)
begin
red<=0;
green<=0;
blue<=0;
end
else
begin
if(red_flag) //红
begin
red<=7;
green<=0;
blue<=0;
end
elseif(blue_flag)//蓝
begin
red<=0;
green<=0;
blue<=7;
end
else if(gren_flag) //绿
begin
red<=0;
green<=0;
blue<=0;
end
else if(doutb)//黑
begin
red<=0;
green<=0;
blue<=0;
end
//画网格
else if(((v_conter==453|v_conter==393|v_conter==333|v_conter==213|v_conter==153|v_conter==93))|((h_conter==115|h_conter==179|h_conter==243|h_conter==307|h_conter==435|h_conter==499|h_conter==563|h_conter==627)))//画网格
begin
red<=5;
green<=5;
blue<=5;
end
else if((h_conter%8 !=0&&v_conter==273)|(v_conter%8 !=0&&h_conter==371))
begin
red<=3;
green<=3;
blue<=3;
end
else//白
begin
red<=7;
green<=7;
blue<=7;
end
end
endmodule
//////////////////////////////////////////////////key.v
//PS2 keyboard
`timescale 1ns / 1ps
module ps2scan(clk,rst_n,ps2k_clk,ps2k_data,ps2_byte,ps2_state);
input clk; //50M时钟信号
input rst_n; //复位信号
input ps2k_clk; //PS2接口时钟信号
input ps2k_data; //PS2接口数据信号
output ps2_byte; // 1byte键值，只做简单的按键扫描
output ps2_state; //键盘当前状态，ps2_state=1表示有键被按下
//------------------------------------------
reg ps2k_clk_r0,ps2k_clk_r1,ps2k_clk_r2; //ps2k_clk状态寄存器
//wire pos_ps2k_clk; // ps2k_clk上升沿标志位
wire neg_ps2k_clk; // ps2k_clk下降沿标志位
always @ (posedge clk or negedge rst_n) begin
if(!rst_n) begin
ps2k_clk_r0 <= 1'b0;
ps2k_clk_r1 <= 1'b0;
ps2k_clk_r2 <= 1'b0;
end
else begin //锁存状态，进行滤波
ps2k_clk_r0 <= ps2k_clk;
ps2k_clk_r1 <= ps2k_clk_r0;
ps2k_clk_r2 <= ps2k_clk_r1;
end
end
assign neg_ps2k_clk = ~ps2k_clk_r1 & ps2k_clk_r2; //下降沿
//------------------------------------------
reg ps2_byte_r; //PC接收来自PS2的一个字节数据存储器
reg temp_data; //当前接收数据寄存器
reg num; //计数寄存器
always @ (posedge clk or negedge rst_n) begin
if(!rst_n) begin
num <= 4'd0;
temp_data <= 8'd0;
end
else if(neg_ps2k_clk) begin //检测到ps2k_clk的下降沿
case (num)
4'd0: num <= num+1'b1;
4'd1: begin
num <= num+1'b1;
temp_data <= ps2k_data; //bit0
end
4'd2: begin
num <= num+1'b1;
temp_data <= ps2k_data; //bit1
end
4'd3: begin
num <= num+1'b1;
temp_data <= ps2k_data; //bit2
end
4'd4: begin
num <= num+1'b1;
temp_data <= ps2k_data; //bit3
end
4'd5: begin
num <= num+1'b1;
temp_data <= ps2k_data; //bit4
end
4'd6: begin
num <= num+1'b1;
temp_data <= ps2k_data; //bit5
end
4'd7: begin
num <= num+1'b1;
temp_data <= ps2k_data; //bit6
end
4'd8: begin
num <= num+1'b1;
temp_data <= ps2k_data; //bit7
end
4'd9: begin
num <= num+1'b1; //奇偶校验位，不做处理
end
4'd10: begin
num <= 4'd0; // num清零
end
default: ;
endcase
end
end
reg key_f0; //松键标志位，置1表示接收到数据8'hf0，再接收到下一个数据后清零
reg ps2_state_r; //键盘当前状态，ps2_state_r=1表示有键被按下
always @ (posedge neg_ps2k_clk or negedge rst_n) begin //接收数据的相应处理，这里只对1byte的键值进行处理
if(!rst_n) begin
key_f0 <= 1'b0;
ps2_state_r <= 1'b0;
end
else if(num==4'd10) begin //刚传送完一个字节数据
if(temp_data == 8'hf0) begin key_f0 <= 1'b1;ps2_state_r <= 1'b0; ps2_byte_r <= 0;end
else begin
if(!key_f0) begin //说明有键按下
ps2_state_r <= 1'b1;
ps2_byte_r <= temp_data; //锁存当前键值
end
else begin
ps2_state_r <= 1'b0;
key_f0 <= 1'b0;
ps2_byte_r <= 0;
end
end
end
end
reg ps2_asci; //接收数据的相应ASCII码
always @ (ps2_byte_r) begin
case (ps2_byte_r) //键值转换为ASCII码，这里做的比较简单，只处理字母(小写)
8'h15: ps2_asci <= 8'h51; //Q
8'h1d: ps2_asci <= 8'h57; //W
8'h24: ps2_asci <= 8'h45; //E
8'h2d: ps2_asci <= 8'h52; //R
8'h2c: ps2_asci <= 8'h54; //T
8'h35: ps2_asci <= 8'h59; //Y
8'h3c: ps2_asci <= 8'h55; //U
8'h43: ps2_asci <= 8'h49; //I
8'h44: ps2_asci <= 8'h4f; //O
8'h4d: ps2_asci <= 8'h50; //P
8'h1c: ps2_asci <= 8'h41; //A
8'h1b: ps2_asci <= 8'h53; //S
8'h23: ps2_asci <= 8'h44; //D
8'h2b: ps2_asci <= 8'h46; //F
8'h34: ps2_asci <= 8'h47; //G
8'h33: ps2_asci <= 8'h48; //H
8'h3b: ps2_asci <= 8'h4a; //J
8'h42: ps2_asci <= 8'h4b; //K
8'h4b: ps2_asci <= 8'h4c; //L
8'h1z: ps2_asci <= 8'h5a; //Z
8'h22: ps2_asci <= 8'h58; //X
8'h21: ps2_asci <= 8'h43; //C
8'h2a: ps2_asci <= 8'h56; //V
8'h32: ps2_asci <= 8'h42; //B
8'h31: ps2_asci <= 8'h4e; //N
8'h3a: ps2_asci <= 8'h4d; //M
8'h75: ps2_asci <= 8'h57; //UP-W
8'h74: ps2_asci <= 8'h44; //R-D
8'h6b: ps2_asci <= 8'h41; //L-A
8'h72: ps2_asci <= 8'h53; //Down-S
8'h16: ps2_asci <= 49; //1
8'h1e: ps2_asci <= 50; //2
8'h26: ps2_asci <= 51; //3
8'h25: ps2_asci <= 52; //4
8'h2e: ps2_asci <= 53; //5
8'h36: ps2_asci <= 54; //6
8'h3d: ps2_asci <= 55; //7
8'h3e: ps2_asci <= 56; //8
8'h46: ps2_asci <= 57; //9
8'h45: ps2_asci <= 48; //0
8'h76: ps2_asci <= 8'hff; //ESC
8'h29: ps2_asci <=32; //' '
default: ps2_asci <= 8'h00; //0;
endcase
end
assign ps2_byte = ps2_asci;
assign ps2_state = ps2_state_r;
endmodule
////////////////////////////////////////////////AD_sample_Ctrl
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//拉高再拉低sam_start开始1次转换，转换完成后addra为1600，作为标志
//////////////////////////////////////////////////////////////////////////////////
module AD_Sample_Ctrl(clk100M,sam_startin,clkdivid,sam_clk,ad_addra,trig_now,sam_clk_out);
input clk100M,sam_startin,trig_now;
input clkdivid;
output reg sam_clk;
output reg ad_addra;
reg count;
reg data;
wire sam_start;
assign sam_start=trig_now|sam_startin;//
always@(clk100M)//频率设置
begin
case(clkdivid)
3'h1:data=25'd2; //32M（33.3M） 刻度应是2us，软件拉成1us
3'h2:data=25'd15;//3.125M
3'h3:data=25'd155;//322.58K
3'h4:data=25'd1562; //32.01K 刻度1ms
3'h5:data=25'd15624; //3.2K
3'h6:data=25'd156249; //320Hz
3'h7:data=25'd1562499; //32Hz(33.3Hz) 1s
default:data=25'd0; //50M
endcase
end
reg sam_clk_32K;
output reg sam_clk_out;
always@(posedge clk100M)
begin
if(clkdivid==6|clkdivid==7)
sam_clk_out<=sam_clk_32K;
else
sam_clk_out<=sam_clk;
end
always @(posedge clk100M)
begin
if(count==data)
begin
sam_clk<=~sam_clk;
count<=0;
end
else
begin
count<=count+1;
end
if(count%12'd2048==0)//有问题
sam_clk_32K<=~sam_clk_32K;
end
reg sam_start0;
reg sam_delay;
reg sam_stop;
always @ (posedge sam_clk)
begin
sam_start0 <= sam_start;
end
always@(posedge sam_clk)
begin
if(sam_start==1&sam_start0==0) //拉高了sam_start
begin sam_delay<=0;sam_stop<=1;end
else if(sam_start==0&sam_start0==1&sam_delay==639) //拉低了sam_start
begin sam_delay<=0;sam_stop<=0;end
else if (sam_delay!=639&sam_stop==1)
sam_delay<=sam_delay+1;
end
always@(posedge sam_clk) //模拟，给AD
begin
if(ad_addra==1279)
ad_addra<=0;
else if(sam_delay!=639)
ad_addra<=ad_addra+1;
end
endmodule
////////////////////////////////////////////////Comp_trig.v
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:45:18 09/20/2010
// Design Name:
// Module Name: Comp_trig
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Comp_trig(sam_clk,clk100M,trig_1sa,trig_now,ad_data_reg);
input ad_data_reg;//模拟部分数据，用来比较
input trig_1sa;//单次触发状态标志，CPU拉高等待触发，触发之后保持输出为高。读完数据后CPU拉低，此时输出也拉低
output reg trig_now;
input sam_clk,clk100M;
wire ad_anlog;
assign ad_anlog=ad_data_reg;
reg trig_flag;
always@(posedge sam_clk)
begin
if(ad_anlog>10'd511)
trig_flag<=1;
else
trig_flag<=0;
end
reg r_trig_1sa,r_trig_flag;
always@(posedge sam_clk)
begin
//r_trig_1sa<=trig_1sa;//锁存1个时钟
r_trig_flag<=trig_flag;
end
always@(sam_clk)
begin
if(trig_flag !=r_trig_flag &&trig_1sa) //翻转，触发
trig_now<=1;
else if(trig_1sa==0)//拉低了，结束单次触发状态
trig_now<=0;
end
endmodule
/////////////////////////////////Led_Seg
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:09:24 09/01/2010
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity clk7seg is
Port ( x : inSTD_LOGIC_VECTOR (15 downto 0);
clk : inSTD_LOGIC; --50MHz
clr : inSTD_LOGIC;
a_to_g : outSTD_LOGIC_VECTOR (6 downto 0);
an : outSTD_LOGIC_VECTOR (3 downto 0);
dp : outSTD_LOGIC);
end clk7seg;
architecture Behavioral of clk7seg is
signal s : std_logic_vector (1 downto 0);
signal digit : std_logic_vector (3 downto 0);
signal clkdiv : std_logic_vector (20 downto 0);
signal aen : std_logic_vector (3 downto 0) := "1111";
begin
dp <= '1';
s <= clkdiv(20 downto 19); --片选
process(clr)
begin
if(clr='1') then
clkdiv <= (others => '0');
elsif(rising_edge(clk)) then
clkdiv <= clkdiv + 1;
end if;
end process;
process(aen,s)
begin
an <= "0000";
if(aen(conv_integer(s))='1') then
an(conv_integer(s)) <= '1'; --an(n)为 1 则片选第 n 个数码管
end if;
end process;
process(s)
begin
case s is
when "00" => digit <= x(3 downto 0);
when "01" => digit <= x(7 downto 4);
when "10" => digit <= x(11 downto 8);
when others => digit <= x(15 downto 12); --4 个数码管轮流显示，有延时
end case;
end process;
process(digit)
begin
case digit is
when x"0" => a_to_g <= "1111110";--"0000001";
when x"1" => a_to_g <= "0110000";--"1001111";
when x"2" => a_to_g <= "1101101";--"0010010";
when x"3" => a_to_g <= "1111001";--"0000110";
when x"4" => a_to_g <= "0110011";--"1001100";
when x"5" => a_to_g <= "1011011";--"0100100";
when x"6" => a_to_g <= "1011111";--"0100000";
when x"7" => a_to_g <= "1110000";--"0001111";
when x"8" => a_to_g <= "1111111";--"0000000";
when x"9" => a_to_g <= "1111011";--"0000100";
when x"A" => a_to_g <= "1110111";--"0001000";
when x"B" => a_to_g <= "0011111";--"1100000";
when x"C" => a_to_g <= "1001110";--"0110001";
when x"D" => a_to_g <= "0111101";--"1000010";
when x"E" => a_to_g <= "1001111";--"0110000";
when others => a_to_g <= "1000111";--"0111000";
end case;
end process;
end Behavioral;
///////////////////////////////////////////ClockManger.v
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2009 Xilinx, Inc.All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//
//Command: xaw2verilog -intstyle I:/MPU_VGA_WithANSICode/ipcore_dir/ClockManger.xaw -st ClockManger.v
//Design Name: ClockManger
//Device: xc3s500e-4pq208
// Written for synthesis tool: XST
`timescale 1ns / 1ps
module ClockManger(CLKIN_IN,
CLKIN_IBUFG_OUT,
CLK0_OUT,
CLK2X_OUT);
input CLKIN_IN;
output CLKIN_IBUFG_OUT;
output CLK0_OUT;
output CLK2X_OUT;
wire CLKFB_IN;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire CLK2X_BUF;
wire GND_BIT;
assign GND_BIT = 0;
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
assign CLK0_OUT = CLKFB_IN;
IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
.O(CLKIN_IBUFG));
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(CLKFB_IN));
BUFG CLK2X_BUFG_INST (.I(CLK2X_BUF),
.O(CLK2X_OUT));
DCM_SP DCM_SP_INST (.CLKFB(CLKFB_IN),
.CLKIN(CLKIN_IBUFG),
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(GND_BIT),
.CLKDV(),
.CLKFX(),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(CLK2X_BUF),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(),
.PSDONE(),
.STATUS());
defparam DCM_SP_INST.CLK_FEEDBACK = "1X";
defparam DCM_SP_INST.CLKDV_DIVIDE = 2.0;
defparam DCM_SP_INST.CLKFX_DIVIDE = 1;
defparam DCM_SP_INST.CLKFX_MULTIPLY = 4;
defparam DCM_SP_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
defparam DCM_SP_INST.CLKIN_PERIOD = 20.000;
defparam DCM_SP_INST.CLKOUT_PHASE_SHIFT = "NONE";
defparam DCM_SP_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
defparam DCM_SP_INST.DFS_FREQUENCY_MODE = "LOW";
defparam DCM_SP_INST.DLL_FREQUENCY_MODE = "LOW";
defparam DCM_SP_INST.DUTY_CYCLE_CORRECTION = "TRUE";
defparam DCM_SP_INST.FACTORY_JF = 16'hC080;
defparam DCM_SP_INST.PHASE_SHIFT = 0;
defparam DCM_SP_INST.STARTUP_WAIT = "FALSE";
endmodule
/////////////////////////////MCU_output_contain
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Engineer: LJT
// Create Date: 15:43:15 09/11/2010
// Design Name:
// Module Name: MCU_OutputCantain
//just as a temp of the unused output pins
//////////////////////////////////////////////////////////////////////////////////
module MCU_OutputCantain(
input ioblock,
input mainclk
);
reg io_buf;
always@(posedge mainclk)
io_buf<=ioblock;
endmodule
////////////////////////////////////约束文件
# VGA Connector done
NET "red<0>" LOC = "p153"|IOSTANDARD = LVCMOS33|DRIVE=2 |PULLDOWN;
NET "red<1>" LOC = "p152"|IOSTANDARD = LVCMOS33|DRIVE=2 |PULLDOWN;
NET "red<2>" LOC = "p151"|IOSTANDARD = LVCMOS33|DRIVE=2 |PULLDOWN;
NET "green<0>" LOC = "p150"|IOSTANDARD = LVCMOS33|DRIVE=2 |PULLDOWN;
NET "green<1>" LOC = "p147"|IOSTANDARD = LVCMOS33|DRIVE=2 |PULLDOWN;
NET "green<2>" LOC = "p146"|IOSTANDARD = LVCMOS33|DRIVE=2 |PULLDOWN;
NET "blue<0>"LOC = "p145"|IOSTANDARD = LVCMOS33|DRIVE=2 |PULLDOWN;
NET "blue<1>"LOC = "p144"|IOSTANDARD = LVCMOS33|DRIVE=2 |PULLDOWN;
NET "blue<2>"LOC = "p140"|IOSTANDARD = LVCMOS33|DRIVE=2 |PULLDOWN;
NET "h_sync" LOC = "p139"|IOSTANDARD = LVCMOS33|DRIVE=2 |PULLDOWN;
NET "v_sync" LOC = "p138"|IOSTANDARD = LVCMOS33|DRIVE=2 |PULLDOWN;
#MAX1241 ADC
NET "max1242_sclk"LOC = "p108"|IOSTANDARD = LVCMOS33|DRIVE=2 |PULLDOWN;
NET "max1241_cs"LOC = "p112"|IOSTANDARD = LVCMOS33|DRIVE=2 |PULLDOWN;
NET "max1241_data" LOC = "p113"|IOSTANDARD = LVCMOS33|DRIVE=2 |PULLDOWN;
#EEPROM
NET "gpio_5<0>"LOC = "p122"|IOSTANDARD = LVCMOS33|DRIVE=2 |PULLUP;
NET "gpio_5<1>" LOC = "p126"|IOSTANDARD = LVCMOS33|DRIVE=2 |PULLUP;
#继电器
NET "JiDaQ<0>" LOC = "p49"|IOSTANDARD = LVCMOS33|DRIVE=2 |PULLDOWN;
NET "JiDaQ<1>" LOC = "p40"|IOSTANDARD = LVCMOS33|DRIVE=2 |PULLDOWN;
NET "JiDaQ<2>" LOC = "p42"|IOSTANDARD = LVCMOS33|DRIVE=2 |PULLDOWN;
NET "JiDaQ<3>" LOC = "p47"|IOSTANDARD = LVCMOS33|DRIVE=2 |PULLDOWN;
#数字信号输入
NET "digt_in<0>" LOC = "p98"|IOSTANDARD = LVCMOS33|DRIVE=2 |PULLDOWN;#P8的1脚
NET "digt_in<1>" LOC = "p99"|IOSTANDARD = LVCMOS33|DRIVE=2 |PULLDOWN;#2脚
#数字信号输出
NET "digt_a" LOC = "p97"|IOSTANDARD = LVCMOS33|DRIVE=2 |PULLDOWN;#3脚
NET "digt_b" LOC = "p94"|IOSTANDARD = LVCMOS33|DRIVE=2 |PULLDOWN;#4脚
#并行AD
NET "sam_clk_out" LOC = "p55"|IOSTANDARD = LVCMOS33|DRIVE=2 |PULLDOWN; #J5,1
NET "ad_data<0>" LOC ="p61"|IOSTANDARD = LVCMOS33|DRIVE=2 |PULLDOWN;#J6
NET "ad_data<1>" LOC ="p63" |IOSTANDARD = LVCMOS33|DRIVE=2 |PULLDOWN;
NET "ad_data<2>" LOC ="p65" |IOSTANDARD = LVCMOS33|DRIVE=2 |PULLDOWN;
NET "ad_data<3>" LOC ="p69"|IOSTANDARD = LVCMOS33 |DRIVE=2 |PULLDOWN;
NET "ad_data<4>" LOC ="p74"|IOSTANDARD = LVCMOS33|DRIVE=2 |PULLDOWN;
NET "ad_data<5>" LOC ="p76"|IOSTANDARD = LVCMOS33|DRIVE=2 |PULLDOWN;
NET "ad_data<6>" LOC ="p78"|IOSTANDARD = LVCMOS33|DRIVE=2 |PULLDOWN;
NET "ad_data<7>" LOC ="p82"|IOSTANDARD = LVCMOS33|DRIVE=2 |PULLDOWN;
NET "ad_data<8>" LOC ="p84"|IOSTANDARD = LVCMOS33|DRIVE=2 |PULLDOWN;
NET "ad_data<9>" LOC ="p89"|IOSTANDARD = LVCMOS33 |DRIVE=2 |PULLDOWN;
# PS/2 connector done
NET "ps2k_clk" LOC = "p22"|IOSTANDARD = LVCMOS33; # Bank = 1, Pin name = IO_L07P_3/LHCLK0, Type = I/O, Sch name = PS2_CLK
NET "ps2k_data" LOC = "p19"|IOSTANDARD = LVCMOS33; # Bank = 1, Pin name = IO_L06N_3, Type = I/O, Sch name = PS2_DATA
#外设
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<7> LOC=p33|IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<6> LOC=p31|IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<5> LOC=p30|IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<4> LOC=p29|IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<3> LOC=p28|IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<2> LOC=p25|IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<1> LOC=p24|IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<0> LOC=p23|IOSTANDARD = LVCMOS33;
Net fpga_0_Push_Buttons_4Bit_GPIO_IO_I_pin<3> LOC=p58|IOSTANDARD = LVCMOS33;
Net fpga_0_Push_Buttons_4Bit_GPIO_IO_I_pin<2> LOC=p57|IOSTANDARD = LVCMOS33;
Net fpga_0_Push_Buttons_4Bit_GPIO_IO_I_pin<1> LOC=p54|IOSTANDARD = LVCMOS33;
Net fpga_0_Push_Buttons_4Bit_GPIO_IO_I_pin<0> LOC=p51|IOSTANDARD = LVCMOS33;
Net fpga_0_Switches_8Bit_GPIO_IO_I_pin<7> LOC=p43|IOSTANDARD = LVCMOS33;
Net fpga_0_Switches_8Bit_GPIO_IO_I_pin<6> LOC=p32|IOSTANDARD = LVCMOS33;
Net fpga_0_Switches_8Bit_GPIO_IO_I_pin<5> LOC=p26|IOSTANDARD = LVCMOS33;
Net fpga_0_Switches_8Bit_GPIO_IO_I_pin<4> LOC=p20|IOSTANDARD = LVCMOS33;
Net fpga_0_Switches_8Bit_GPIO_IO_I_pin<3> LOC=p14|IOSTANDARD = LVCMOS33;
Net fpga_0_Switches_8Bit_GPIO_IO_I_pin<2> LOC=p6|IOSTANDARD = LVCMOS33;
Net fpga_0_Switches_8Bit_GPIO_IO_I_pin<1> LOC=p204|IOSTANDARD = LVCMOS33;
Net fpga_0_Switches_8Bit_GPIO_IO_I_pin<0> LOC=p194|IOSTANDARD = LVCMOS33;
Net fpga_0_RS232_PORT_RX_pin LOC=p184|IOSTANDARD = LVCMOS33|PULLUP;
Net fpga_0_RS232_PORT_TX_pin LOC=p18|IOSTANDARD = LVCMOS33|DRIVE = 2;
#RAM
Net fpga_0_Micron_RAM_Mem_A_pin<31> LOC=p178|IOSTANDARD = LVCMOS33|DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<30> LOC=p193|IOSTANDARD = LVCMOS33|DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<29> LOC=p196|IOSTANDARD = LVCMOS33|DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<28> LOC=p197|IOSTANDARD = LVCMOS33|DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<27> LOC=p199|IOSTANDARD = LVCMOS33|DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<26> LOC=p200|IOSTANDARD = LVCMOS33|DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<25> LOC=p202|IOSTANDARD = LVCMOS33|DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<24> LOC=p203|IOSTANDARD = LVCMOS33|DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<23> LOC=p4|IOSTANDARD = LVCMOS33|DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<22> LOC=p5|IOSTANDARD = LVCMOS33|DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<21> LOC=p8|IOSTANDARD = LVCMOS33|DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<20> LOC=p9|IOSTANDARD = LVCMOS33|DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<19> LOC=p11|IOSTANDARD = LVCMOS33|DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<18> LOC=p12|IOSTANDARD = LVCMOS33|DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<17> LOC=p15|IOSTANDARD = LVCMOS33|DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<16> LOC=p16|IOSTANDARD = LVCMOS33|DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<15> LOC=p160|IOSTANDARD = LVCMOS33|DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<14> LOC=p205|IOSTANDARD = LVCMOS33|DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<13> LOC=p206|IOSTANDARD = LVCMOS33|DRIVE=2;
Net fpga_0_Micron_RAM_Mem_CEN_pin LOC=p192|IOSTANDARD = LVCMOS33|DRIVE=2|PULLUP;
Net fpga_0_Micron_RAM_Mem_OEN_pin LOC=p180|IOSTANDARD = LVCMOS33|DRIVE=2|PULLUP;
Net fpga_0_Micron_RAM_Mem_WEN_pin LOC=p2|IOSTANDARD = LVCMOS33|DRIVE=2;
Net fpga_0_Micron_RAM_Mem_BEN_pin<0> LOC=p135|IOSTANDARD = LVCMOS33|DRIVE=2|PULLDOWN;
Net fpga_0_Micron_RAM_Mem_BEN_pin<1> LOC=p134|IOSTANDARD = LVCMOS33|DRIVE=2|PULLDOWN;
Net fpga_0_Micron_RAM_Mem_DQ_pin<15> LOC=p181|IOSTANDARD = LVCMOS33|DRIVE=2;
Net fpga_0_Micron_RAM_Mem_DQ_pin<14> LOC=p186|IOSTANDARD = LVCMOS33|DRIVE=2;
Net fpga_0_Micron_RAM_Mem_DQ_pin<13> LOC=p177|IOSTANDARD = LVCMOS33|DRIVE=2;
Net fpga_0_Micron_RAM_Mem_DQ_pin<12> LOC=p190|IOSTANDARD = LVCMOS33|DRIVE=2;
Net fpga_0_Micron_RAM_Mem_DQ_pin<11> LOC=p171|IOSTANDARD = LVCMOS33|DRIVE=2;
Net fpga_0_Micron_RAM_Mem_DQ_pin<10> LOC=p167|IOSTANDARD = LVCMOS33|DRIVE=2;
Net fpga_0_Micron_RAM_Mem_DQ_pin<9> LOC=p164|IOSTANDARD = LVCMOS33|DRIVE=2;
Net fpga_0_Micron_RAM_Mem_DQ_pin<8> LOC=p162|IOSTANDARD = LVCMOS33|DRIVE=2;
Net fpga_0_Micron_RAM_Mem_DQ_pin<7> LOC=p185|IOSTANDARD = LVCMOS33|DRIVE=2;
Net fpga_0_Micron_RAM_Mem_DQ_pin<6> LOC=p187|IOSTANDARD = LVCMOS33|DRIVE=2;
Net fpga_0_Micron_RAM_Mem_DQ_pin<5> LOC=p189|IOSTANDARD = LVCMOS33|DRIVE=2;
Net fpga_0_Micron_RAM_Mem_DQ_pin<4> LOC=p172|IOSTANDARD = LVCMOS33|DRIVE=2;
Net fpga_0_Micron_RAM_Mem_DQ_pin<3> LOC=p168|IOSTANDARD = LVCMOS33|DRIVE=2;
Net fpga_0_Micron_RAM_Mem_DQ_pin<2> LOC=p165|IOSTANDARD = LVCMOS33|DRIVE=2;
Net fpga_0_Micron_RAM_Mem_DQ_pin<1> LOC=p163|IOSTANDARD = LVCMOS33|DRIVE=2;
Net fpga_0_Micron_RAM_Mem_DQ_pin<0> LOC=p161|IOSTANDARD = LVCMOS33|DRIVE=2;
Net clk TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 50000 kHz;
Net clk LOC=p80|IOSTANDARD = LVCMOS33;
Net fpga_0_rst_1_sys_rst_pin TIG;
Net fpga_0_rst_1_sys_rst_pin LOC=p71|IOSTANDARD = LVCMOS33;
////////////////////////////////////.c文件
#include "xparameters.h"
#include "xgpio.h"
#include "chars.c"
void writestring(unsigned int x,unsigned int y,unsigned char *asc) //x:0-9;32bitX12直接输出string,5个
{
unsigned long tmp;
unsigned long tmpaddr;
unsigned char j; unsigned char m,n,o,p,q;
m=*(asc++)-48;
n=*(asc++)-48;
o=*(asc++)-48;
p=*(asc++)-48;
q=*asc-48;
unsigned char *temp={chars,chars,chars,chars,chars};
temp+=m*12;temp+=n*12;temp+=o*12;temp+=p*12;temp+=q*12;
for(j=0;j<12;j++)
{
tmp=0;
tmp|=((unsigned long)(*temp))<<24;
tmp|=((unsigned long)(*temp))<<18;
tmp|=((unsigned long)(*temp))<<12;
tmp|=((unsigned long)(*temp))<<6;
tmp|=((unsigned long)(*temp));
tmpaddr=(unsigned long)((y+j)*10+x);
XGpio_DiscreteWrite (&addr12, 1, tmpaddr);
XGpio_DiscreteWrite (&data32, 1, tmp);
temp++;temp++;temp++;temp++;temp++;
}
}
void drict_vga_putnum(unsigned int x,unsigned int y,unsigned long value) //32bitX12直接输出uint，限大小99999
{ //原有的图形将被覆盖,y:0-9
uchar tmp;
tmp=(value%100000)/10000+48;
tmp=(value%10000)/1000+48;
tmp=(value%1000)/100+48;
tmp=(value%100)/10+48;
tmp=value%10+48;
writestring(x,y,tmp);
}
void ClrScn()//清屏
{
ulong i,j;
for(i=0;i<240;i++) //清RAM
{
for(j=0;j<10;j++)
{
XGpio_DiscreteWrite (&addr12, 1, i*10+j);
XGpio_DiscreteWrite (&data32, 1, 0);
}
}
}
void draw_wave()
{
ulong j,tmp=0;
ulong ddp1,ddp2,rt;
int offset_add;
long tmp2;
uint sb;
if(sam_clk_slect>>23==1) sb=2;
else sb=1;
for(j=0;j<320;j++)
{
tmp=0;
if(ch2_show)
{
if(fft_data&0x0001) ddp1=20;//通道2
else ddp1=100;
tmp|=ddp1;//黑
}
if(ch3_show)
{
if(fft_data&0x0002) //通道2
ddp1=138;
else ddp1=219;
tmp|=ddp1<<16;//蓝
}
if(ch1_show)
{
if(vot_flag==3) offset_add=430;//最小量程1mv时的补偿措施
else if(vot_flag==2) offset_add=6;//10mV的补偿措施
else offset_add=0;
if(vot_flag==3) rt=2;
else rt=4;
if(sam_clk_slect>>23==1)//最高档位，插值算法
{
if(j%2==0)
{
tmp2=((ulong)(119-(fft_data>>rt)+ch1_offset+offset_add));//红
if(tmp2>238) tmp2=239;//嵌位
if(tmp2<1) tmp2=0;
tmp|=tmp2<<8;
}
else
{tmp2=((ulong)(119-((fft_data>>(rt+1))+(fft_data>>(rt+1)))+ch1_offset+offset_add));
if(tmp2>238) tmp2=239;
if(tmp2<1) tmp2=0;
tmp|=tmp2<<8;
}
}
else //普通档位
{
tmp2=((ulong)(119-(fft_data>>rt)+ch1_offset+offset_add));//红
if(tmp2>238) tmp2=239;
if(tmp2<1) tmp2=0;
tmp|=tmp2<<8;
}
}
XGpio_DiscreteWrite (&addr12, 1, j+4096);
XGpio_DiscreteWrite (&data32, 1,tmp );//
}
}
void recall()
{
uint i,addh,j;
uint tmp1,tmp2;
uint oft_x=160;
ulong tmp;
ClrScn();
delay_ms(50);
for(addh=0;addh<40;addh++)
{
for(i=0;i<16;i++) //读n个字节数据
{
start_24c64();
writebyte_24c64(0xa0);//写指令
writebyte_24c64(2*i);//写高位地址
writebyte_24c64(addh);//写低位地址(实际上是调24c64地址指针到要读取的数据的地址)
stop_24c64();
start_24c64();
writebyte_24c64(0xa1);//写读指令
tmp1 =readbyte_24c64();
stop_24c64();
delay_us(100);
start_24c64();
writebyte_24c64(0xa0);//写指令
writebyte_24c64(2*i+1);//写高位地址
writebyte_24c64(addh);//写低位地址(实际上是调24c64地址指针到要读取的数据的地址)
stop_24c64();
start_24c64();
writebyte_24c64(0xa1);//写读指令
tmp2 = readbyte_24c64();
stop_24c64();
delay_us(100);
fft_data=(tmp1<<8)|tmp2;
}
}
while(1)
{
for(j=0;j<320;j++) //画图
{
tmp=0;
tmp|=(ulong)(239-(fft_data>>4))<<8;
XGpio_DiscreteWrite (&addr12, 1, j+4096);
XGpio_DiscreteWrite (&data32, 1,tmp );
}
//波形x方向上平移
j=(uchar)(XGpio_DiscreteRead (&kb9, 1));
if(j=='A') {if(oft_x!=0) oft_x--;}
if(j=='D') {if(oft_x!=320) oft_x++;}
if(j==' ') break;
delay_ms(8);
}
}
void write_eep()
{
uchar str_doing[]="Sving";
uint i,addh;uint tmp;
writestring(1,2,str_doing);
for(addh=0;addh<40;addh++)//写fftdata[],640个16位数据
{
for(i=0;i<16;i++)
{
start_24c64();
writebyte_24c64(0xa0);//写指令
writebyte_24c64(2*i);//写高位地址
writebyte_24c64(addh);//写低位地址
delay_us(10);
tmp=fft_data>>8;//(uchar)(
writebyte_24c64(tmp);//写高8位
stop_24c64();
delay_ms(2);
start_24c64();
writebyte_24c64(0xa0);//写指令
writebyte_24c64(2*i+1);//写高位地址
writebyte_24c64(addh);//写低位地址
delay_us(10);
tmp=(uchar)(fft_data&0x00ff);
writebyte_24c64(tmp);//写低8位
stop_24c64();
delay_ms(2);
}
}
ClrScn();
}
void adc_sample12bit()
{
long i,j,addra;long tmp,oft=0;
uchar str_pos[]="Pos:_";
if(trig_1sa==0)//平常的采样时序
{
XGpio_DiscreteWrite (&gpio4, 1, (1<<22)|markline|sam_clk_slect);//拉高Samstart
XGpio_DiscreteWrite (&gpio4, 1, markline|sam_clk_slect);//拉低Samstart
XGpio_DiscreteWrite (&gpio4, 1,(1<<22)|markline|sam_clk_slect);//拉高Samstart
XGpio_DiscreteWrite (&gpio4, 1, markline|sam_clk_slect);//拉低Samstart
XGpio_DiscreteWrite (&gpio4, 1,(1<<22)|markline|sam_clk_slect);//拉高Samstart
j=0;
}
else //单次触发，存储显示时的时序
{
XGpio_DiscreteWrite (&gpio4, 1, (1<<26)|markline|sam_clk_slect);//拉高Samstart
XGpio_DiscreteWrite (&gpio4, 1, markline|sam_clk_slect);//拉高Samstart
XGpio_DiscreteWrite (&gpio4, 1, (1<<26)|markline|sam_clk_slect);//拉高Samstart
j=-6553555;
}
while(1)//等待完成
{
j++;
addra=XGpio_DiscreteRead(&fft32, 1)>>12;
switch(sam_clk_slect>>23)
{
case 7:delay_ms(100);break;
default:delay_ms(10);break;
}
i=XGpio_DiscreteRead (&kb9, 1);
if(i=='V'+256){save_flag=1;writestring(8,3,str_save);}
if(i=='L'+256||i=='J'+256) break;
if((sam_clk_slect>>23)<4&&j>30) break;//防止出错，程序假死
{if(addra==XGpio_DiscreteRead(&fft32, 1)>>12)break;}
//drict_vga_putnum(6,2,addra);
}
if(save_flag||trig_1sa)//存储或是存储显示
{
ch1_show=1;ch2_show=0;ch3_show=0;offset_x=0;
ClrScn();
if(delay_time>1000) { addra=addra-(delay_time-1481);if(addra>1279) addra-=1279;if(addra<0) addra+=1279;}
else{addra=addra+delay_time+481;if(addra>1279) addra-=1279;if(addra<0) addra+=1279;}
delay_ms(300);
while(1)
{
writestring(8,2,str_pos);
drict_vga_putnum(9,2,oft+480);
for(j=0;j<640;j++)
{
tmp=j+addra+oft;if(tmp>1279) tmp-=1280;if(tmp<0) tmp+=1280;
XGpio_DiscreteWrite (&gpio4, 1, (trig_1sa<<26)|(1<<22)|tmp<<11|markline|sam_clk_slect);//输入地址
fft_data=(uint)(0x0fff&XGpio_DiscreteRead (&fft32, 1));//提取低12位
}
i=XGpio_DiscreteRead (&kb9, 1);
//波形x方向上平移
if(i=='A'+256) {oft--;drict_vga_putnum(9,3,oft+480);}
if(i=='D'+256) {oft++;drict_vga_putnum(9,3,oft+480);}
draw_wave();
if(oft>489) oft=489;//移动范围+-160共两屏；正负时延480点
if(oft<-489) oft=-489;
if(i==' '+256) {break; }
//手动存储功能
if(i=='U'+256) write_eep();
delay_ms(4);
}
delay_ms(500);ClrScn();
save_flag=0;
}
else
{
for(j=0;j<320;j++)//触发
{
tmp=j+addra+1;if(tmp>1279) tmp-=1280;
XGpio_DiscreteWrite (&gpio4, 1, (1<<22)|tmp<<11|markline|sam_clk_slect);//输入地址
if(trig_dir)//上升沿
{
if(trig_res==2) {fft_data=(uint)(0x01&XGpio_DiscreteRead (&fft32, 1));if(j>3&&fft_data==0&&fft_data==0&&fft_data) break;}
//模拟通道触发
if(trig_res==1)
{
fft_data=((uint)(XGpio_DiscreteRead (&fft32, 1))&0x0fff)>>2;//>>4
if(j>5&&fft_data>v_trig*4&&fft_data>v_trig*4&&fft_data>=v_trig*4&&fft_data<v_trig*4&&fft_data<v_trig*4&&fft_data<v_trig*4) break;
}
if(trig_res==3) {fft_data=(uint)(0x02&XGpio_DiscreteRead (&fft32, 1));if(j>3&&fft_data==0&&fft_data==0&&fft_data) break;}
}
else //下降沿
{
if(trig_res==2) {fft_data=(uint)(0x01&XGpio_DiscreteRead (&fft32, 1));if(j>3&&fft_data==1&&fft_data==1&&fft_data==0) break;}
//模拟通道触发
if(trig_res==1)
{
fft_data=((uint)(XGpio_DiscreteRead (&fft32, 1))&0x0fff)>>2;//>>4
if(j>5&&fft_data<v_trig*4&&fft_data<v_trig*4&&fft_data<=v_trig*4&&fft_data>v_trig*4&&fft_data>v_trig*4&&fft_data>v_trig*4) break;
}
if(trig_res==3) {fft_data=(uint)(0x02&XGpio_DiscreteRead (&fft32, 1));if(j>3&&fft_data&&fft_data&&fft_data==0) break;}
}
}
for(i=0;i<640;i++)
{ tmp=i+j+addra+1;if(tmp>1279) tmp-=1280;
XGpio_DiscreteWrite (&gpio4, 1, (1<<22)|tmp<<11|markline|sam_clk_slect);//输入地址
fft_data=(uint)(0x0fff&XGpio_DiscreteRead (&fft32, 1));//提取低12位
}
}
trig_1sa=0;
XGpio_DiscreteWrite (&gpio4, 1, markline|sam_clk_slect);//拉低Samstart
}
void sort(ulong *asc)//排序函数
{ulong i,j,tmp;
for(i=0;i<9;i++)
{
for(j=i+1;j<=9;j++)
if(*(asc+i)>*(asc+j)) {tmp=*(asc+i);*(asc+i)=*(asc+j);*(asc+j)=tmp;}
}
}
ulong ans_10;
void measure()
{
static uint kk;
static ulong amax,amin,af,avpp,max,min,t;
uintj=0,i;
uchar strtmp;
static ulong aPrd;
uchar str1[]="_T=__";
uchar str2[]="Vmn=_";
uchar str3[]="Vpp=_";
uchar str4[]="frq=_";
max=0;
min=1024;
for (i=1; i<640;i++)
{
if(max<=fft_data>>2) max=fft_data>>2;
if(min>=fft_data>>2) min=fft_data>>2;
}
max=max*VREF/960;//换算成电压，单位mV
min=min*VREF/960;
t=XGpio_DiscreteRead (&gpio7, 1); //T
kk++;
if(kk>=10)//10次处理一次//从10个t和Vmax和min之间找到他的中值！
{
sort(max);sort(min);sort(t);
ans_10=t;
amax=max; //选取偏小一点的
amin=min;
avpp=amax-amin;
kk=0;
//电压
str3=(avpp%10000)/1000+48;
strtmp=(avpp%1000)/100+48;
strtmp=(avpp%100)/10+48;
strtmp=avpp%10+48;
strtmp='m';
strtmp='V';
writestring(6,227,str3); writestring(7,227,strtmp);
//周期
if(ans_10<9999) {aPrd=ans_10*10;strtmp='n';strtmp='s';}//单位：ns
else if(ans_10<9999000) {aPrd=ans_10/100;strtmp='u';strtmp='s';}//us
else {aPrd=ans_10/100000;strtmp='m';strtmp='s';}//ms
if(aPrd>9999) str1=(aPrd/10000)+48;//万位，占了'='
str1=(aPrd%10000)/1000+48;
strtmp=(aPrd%1000)/100+48;
strtmp=(aPrd%100)/10+48;
strtmp=aPrd%10+48;
writestring(0,227,str1); writestring(1,227,strtmp);
//频率
if(ans_10<10000) {strtmp='K';strtmp='_';}
else{ans_10/=1000;strtmp='H';strtmp='z';}
af=100000/ans_10;
if(af>9999) str4=(af/10000)+48;//万位，占了'='
str4=(af%10000)/1000+48;
strtmp=(af%1000)/100+48;
strtmp=(af%100)/10+48;
strtmp=af%10+48;
writestring(3,227,str4); writestring(4,227,strtmp);
if(strtmp=='H') ans_10*=1000;
}
}
void AutoSet()
{
int i;
ulong m;
ulong j;
uchar str_a[]="Auto_";
uchar str_b[]="Set``";
uint Vmax=0,Vmin=1024;
uint tt;
uint t;
sam_clk_slect=4<<23;//10ms档位测幅值
ClrScn();
writestring(1,1,str_a);
writestring(2,1,str_b);
delay_ms(100);
adc_sample12bit();
for(m=0;m<4;m++)//自动量程选择
{
vot_flag=m; set_vot();adc_sample12bit();
delay_ms(100);
adc_sample12bit();
Vmax=0,Vmin=1024;
//寻找最大最小值
for (i=5; i<560;i++){if(Vmax<(fft_data>>2)) Vmax=(fft_data>>2); if(Vmin>(fft_data>>2)) Vmin=fft_data>>2;}
if(Vmax>580||Vmin<380) break;//480中值，左右超过100（1024的1/10）为准
}
v_trig=(Vmax+Vmin)/8;
for(m=1;m<7;m++)//自动扫描速率
{
sam_clk_slect=(m<<23);
delay_ms(300);
adc_sample12bit();
delay_ms(300);
adc_sample12bit();
j=0;
tt=0;tt=0;
for (i=240; i<640;i++)
{
if(((fft_data>>2)>v_trig*4) && ((fft_data>>2)>=v_trig*4) &&((fft_data>>2) <= v_trig*4) && ((fft_data>>2) < v_trig*4) )
{
if(j<2) {if(j==0||i>tt+3) {tt=i; j++;}}
else break;
}
}
t=tt-tt; drict_vga_putnum(18,4,t);
draw_wave();
if(((t>9&&m==1)||(t>25))&&t<320) break;
}
ClrScn();
operat_delay_cnt=1;markline=(239-v_trig)<<3;
}
write_trg()
{
long vl;
uchar str1[]="trig_";
uchar str2[]="levl:";
uchar str3[]="_____";
uchar str4[]="mV___";
vl=(121-(markline>>3));//换算成电压，单位mVmarkline>>3)
if(vl<0) {str3='^';vl=-vl;}
else str3='_';
vl=vl*VREF/240;
if(vot_flag==3) vl/=4;
str3=(vl%10000)/1000+48;
str3=(vl%1000)/100+48;
str3=(vl%100)/10+48;
str3=vl%10+48;
writestring(0,markline>>3,str1);writestring(1,markline>>3,str2);writestring(2,markline>>3,str3);writestring(3,markline>>3,str4);
}
void set_digt()
{
uchar str1[]="__00K";
uchar str2[]="SYNC_";
ulong j;
uchar str3[]="Set_D";
uchar str4[]="igt_C";
uchar str5[]="hanle";
ClrScn();
writestring(1,3,str3);writestring(2,3,str4);writestring(3,3,str5);
delay_ms(200);
freq_ctrl=0;
while(1){j=(uchar)(XGpio_DiscreteRead (&kb9, 1));if(j) break;}
if(j-48) {freq_ctrl+=10;str1='1';}
delay_ms(300);
while(1){j=(uchar)(XGpio_DiscreteRead (&kb9, 1));if(j) break;}
freq_ctrl+=(j-48);
if(freq_ctrl==0) writestring(7,42,str2);
else
{
str1=(freq_ctrl%10)+48; writestring(7,42,str1);
}
XGpio_DiscreteWrite (&gpio6, 1, freq_ctrl);
delay_ms(1000);
ClrScn();
}
void set_time()
{
uchar str1[]="Input";
uchar str2[]="Time:";
uchar str3[]="Press";
uchar str4[]="any_K";
uchar str5[]="ey_Co";
uchar str6[]="nfirm";
uint j;
writestring(1,3,str1);writestring(2,3,str2);
delay_time=0;
while(1){j=XGpio_DiscreteRead (&kb9, 1);if(j) break;} delay_time+=(j-304)*1000;
drict_vga_putnum(18,4,delay_time);delay_ms(500);
while(1){j=XGpio_DiscreteRead (&kb9, 1);if(j) break;} delay_time+=(j-304)*100;
drict_vga_putnum(18,4,delay_time);delay_ms(500);
while(1){j=XGpio_DiscreteRead (&kb9, 1);if(j) break;} delay_time+=(j-304)*10;
drict_vga_putnum(18,4,delay_time);delay_ms(500);
while(1){j=XGpio_DiscreteRead (&kb9, 1);if(j) break;} delay_time+=(j-304);
drict_vga_putnum(18,4,delay_time);delay_ms(500);
delay_ms(500);
writestring(5,200,str3);writestring(6,200,str4); writestring(7,200,str5); writestring(8,200,str6);
while(1){j=XGpio_DiscreteRead (&kb9, 1);if(j) break;}
ClrScn();
if(delay_time<1000) delay_time=delay_time/2;
else delay_time=delay_time/2+500;
}
int main (void)
{
ulong i,j,fftmp;ulong findex;
uint x,y,yhis;
unsigned char str_stop[]="STOP";
uchar str_time[]="]_;_:";//时间
uchar str_t0[]="0`3us";
uchar str_t1[]="1us__";
uchar str_t2[]="10us_";
uchar str_t3[]="100us";
uchar str_t4[]="1ms__";
uchar str_t5[]="10ms_";
uchar str_t6[]="100ms";
uchar str_t7[]="1s___";
uchar str_ch1[]="@:CH1";//红
uchar str_ch2[]="<:CH2";//蓝
uchar str_ch3[]=">:CH3";//黑
uchar str_fudu[]="_?_[:"; //幅度
uchar str_fd0[]="1`0V_";
uchar str_fd1[]="0`1V_";
uchar str_fd2[]="10mV_";
uchar str_fd3[]="1mV__";
XGpio_Initialize (&data32, XPAR_XPS_GPIO_0_DEVICE_ID) ;
XGpio_Initialize (&addr12, XPAR_XPS_GPIO_1_DEVICE_ID) ;
XGpio_Initialize (&led8, XPAR_LEDS_8BIT_DEVICE_ID) ;
XGpio_Initialize (&bot4, XPAR_PUSH_BUTTONS_4BIT_DEVICE_ID) ;
XGpio_Initialize (&kb9, XPAR_XPS_GPIO_2_DEVICE_ID) ;
XGpio_Initialize (&fft32, XPAR_XPS_GPIO_3_DEVICE_ID) ;
XGpio_Initialize (&gpio4, XPAR_XPS_GPIO_4_DEVICE_ID) ;
XGpio_Initialize (&gpio5, XPAR_XPS_GPIO_5_DEVICE_ID);
XGpio_Initialize (&jidaq, XPAR_JIDAQ_DEVICE_ID);
XGpio_Initialize (&gpio6, XPAR_XPS_GPIO_DIGT_CTRL_DEVICE_ID);
XGpio_Initialize (&gpio7, XPAR_XPS_GPIO_FREQ_DEVICE_ID);
XGpio_SetDataDirection (&data32, 1, 0);
XGpio_SetDataDirection (&addr12, 1, 0);
XGpio_SetDataDirection (&led8, 1, 0);
XGpio_SetDataDirection (&bot4, 1, 1);
XGpio_SetDataDirection (&kb9, 1, 1);
XGpio_SetDataDirection (&fft32, 1, 1);
XGpio_SetDataDirection (&gpio4, 1, 0);
XGpio_SetDataDirection (&gpio5, 1, 0);
XGpio_SetDataDirection (&jidaq, 1, 0);
XGpio_SetDataDirection (&gpio6, 1, 0);
XGpio_SetDataDirection (&gpio7, 1, 1);
XGpio_DiscreteWrite (&led8, 1, 0x00);
XGpio_DiscreteWrite (&jidaq, 1, 0);
delay_ms(200);
ClrScn();//清屏
/////////////////////////////////////////////初始化完毕
while(1)
{
delay_ms(200);ClrScn();i=0;
while(1)
{
adc_sample12bit();
delay_ms(20);
draw_wave();
if(m_flag) measure();//测量
writestring(4,2,str_time);//左上角，写时间
switch(sam_clk_slect>>23)
{
case 0:writestring(5,2,str_t0); samp_f=50000;break;
case 1:writestring(5,2,str_t1); samp_f=16666;break;//X1000，频率单位KHz
case 2:writestring(5,2,str_t2); samp_f=3125; break;
case 3:writestring(5,2,str_t3); samp_f=322580;break;
case 4:writestring(5,2,str_t4); samp_f=32010;break;//X1,频率单位Hz
case 5:writestring(5,2,str_t5); samp_f=3200;break;
case 6:writestring(5,2,str_t6); samp_f=320;break;
default:writestring(5,2,str_t7); samp_f=32;break;
}
writestring(0,2,str_fudu);//zuo上角，写幅度
switch(vot_flag)
{
case 0:writestring(1,2,str_fd0); break;
case 1:writestring(1,2,str_fd1); break;
case 2:writestring(1,2,str_fd2); break;
default:writestring(1,2,str_fd3); break;
}
if(ch1_show==1) writestring(9,2,str_ch1);
if(ch2_show==1) writestring(9,16,str_ch2);
if(ch3_show==1) writestring(9,28,str_ch3);
//以下是读取键盘值,响应用户操作
j=(uchar)(XGpio_DiscreteRead (&kb9, 1));
switch(j)
{
//RUN/STOP
case 'R': { XGpio_DiscreteWrite (&led8, 1, 0x00); delay_ms(350);while(1){writestring(9,3,str_stop); j=XGpio_DiscreteRead (&kb9, 1); if(j=='R'+256){delay_ms(200);ClrScn(); break;}}}break;
//切换通道
case '1': {if(ch1_show==1) {ch1_show=0;ClrScn();} else {ch1_act=1;ch1_show=1;} XGpio_DiscreteWrite (&led8, 1, 0x00);delay_ms(200);}break;
case '2': {if(ch2_show==1) {ch2_show=0;ClrScn();} else {ch1_act=1;ch2_show=1;}XGpio_DiscreteWrite (&led8, 1, 0x00); delay_ms(200);}break;
case '3': {if(ch3_show==1) {ch3_show=0;ClrScn();} else ch3_show=1; delay_ms(200);}break;
//触发电平调节
case 'T': {XGpio_DiscreteWrite (&led8, 1, 0x00);v_trig+=1; operat_delay_cnt=1;markline=(239-v_trig)<<3;}break;
case 'G': {XGpio_DiscreteWrite (&led8, 1, 0x00);v_trig-=1; operat_delay_cnt=1;markline=(239-v_trig)<<3;}break;
//波形y方向上平移
case 'W': {if(ch1_act) {ch1_offset-=2;markline=(ch1_offset)<<3;} else {ch2_offset-=2;markline=(ch2_offset)<<3;}operat_delay_cnt=1;}break;
case 'S': {if(ch1_act) {ch1_offset+=2;markline=(ch1_offset)<<3;} else {ch2_offset+=2;markline=(ch2_offset)<<3;}operat_delay_cnt=1;}break;
//波形x方向上平移
case 'A': {offset_x-=2;operat_delay_cnt=1;}break;
case 'D': {offset_x+=2;operat_delay_cnt=1;}break;
//时间档位选择
case 'L': {if(sam_clk_slect!=1<<23) sam_clk_slect-=(1<<23);XGpio_DiscreteWrite (&led8, 1, 0x00);delay_ms(250);}break;
case 'J': {if(sam_clk_slect!=(7<<23)) sam_clk_slect+=(1<<23);XGpio_DiscreteWrite (&led8, 1, 0x00);delay_ms(250);}break;
//垂直量程选择
case 'I': {if(vot_flag!=3) vot_flag++; set_vot();XGpio_DiscreteWrite (&led8, 1, 0x00);delay_ms(250);}break;
case 'K': {if(vot_flag!=0) vot_flag--; set_vot();XGpio_DiscreteWrite (&led8, 1, 0x00);delay_ms(250);}break;
//是否测量
case 'M': {m_flag=!m_flag;XGpio_DiscreteWrite (&led8, 1, 0xff); delay_ms(200);ClrScn(); }break;
//存储和回放
case 'V': {save_flag=1;writestring(8,3,str_save);}break;
//触发源选择
case 'O': {delay_ms(200);trig_res++;if(trig_res==4) trig_res=1;}break;
//上升/下降沿触发切换
case 'P': {XGpio_DiscreteWrite (&led8, 1, 0x00);delay_ms(200);trig_dir=~trig_dir;}break;
//设置存储延时
case 'C': {XGpio_DiscreteWrite (&led8, 1, 0x00);delay_ms(200);ClrScn();set_time();}break;//
//存储显示功能
case 'H': {XGpio_DiscreteWrite (&led8, 1, 0x00);trig_1sa=1;writestring(8,3,str_save);delay_ms(200);}break;
//手动存储功能
case 'U': {ClrScn();XGpio_DiscreteWrite (&led8, 1, 0x00);write_eep();} break;
//ReCall
case 'Y': {recall();XGpio_DiscreteWrite (&led8, 1, 0x00);delay_ms(200);} break;
//设置数字信号
case 'Q': {XGpio_DiscreteWrite (&led8, 1, 0x00);set_digt();delay_ms(250);} break;
//AutoSet
case 'X': {XGpio_DiscreteWrite (&led8, 1, 0x00);AutoSet();delay_ms(250);} break;
}
//延时清除显示
if(operat_delay_cnt) {operat_delay_cnt++;write_trg();}
if(operat_delay_cnt>50) {operat_delay_cnt=0;markline=0;ClrScn();}
XGpio_DiscreteWrite (&gpio6, 1, freq_ctrl);
XGpio_DiscreteWrite (&led8, 1, 0xff);
}
delay_ms(200);ClrScn();
}
}
////////////////////////////chars.c 包含变量定义 部分函数 和用到的字模
#define uint unsigned int
#define ulong unsigned long
#define uchar unsigned char
//全局变量
XGpio data32;
XGpio addr12;
XGpio led8;
XGpio bot4;
XGpio kb9;
XGpio fft32;
XGpio gpio4;
XGpio gpio5;
XGpio gpio6;
XGpio gpio7;
XGpio jidaq;
uint fft_data;
ulong samp_f=50000;//采样率
//OSC显示与操作g变量
uchar ch1_act=1,ch1_show=1,ch2_show=0,ch3_show=0;//CH2为模拟通道
uint v_trig=117;
uint ch1_offset=120;uint ch2_offset=0;
uint markline=0;
int offset_x=0;
uchar m_flag=1;
ulong sam_clk_slect=3<<23;//采样率控制
uchar trig_dir=0xff;//触发边沿选择；0xff上升，0x00下降沿
uchar trig_res=1;//触发源选择
uchar str_save[]="Save";
uint delay_time=0;
uchar save_flag=0;//存储标志
ulong trig_1sa=0;//存储显示标志
ulong freq_ctrl=0;//0跟随，12345678910。。。代表不同的百KHz，defult为100K
uint operat_delay_cnt;
void delay_ms(ulong tim)
{
volatile ulong i,j;
for(j=0;j<tim;j++)
{
for(i=0;i<10000;i++);
}
}
void delay_us(ulong tim)
{
volatile ulong i,j;
for(j=0;j<tim;j++)
{
for(i=0;i<8;i++);
}
}
//放大倍数控制
ulong vot_flag=0;
ulong VREF=8000;//原来是define，所以大写了
void set_vot()
{
switch(vot_flag)
{
case 0:XGpio_DiscreteWrite (&jidaq,1,0x00); VREF=8000; break;//1V/div
case 1:XGpio_DiscreteWrite (&jidaq,1,0x08); VREF=800;break;//100mV/div 增大0.5%
case 2:XGpio_DiscreteWrite (&jidaq,1,0x0c); VREF=80; break;//10mV/div
case 3:XGpio_DiscreteWrite (&jidaq,1,0x0f); VREF=32; break;//2mV/div
default:XGpio_DiscreteWrite (&jidaq,1,0x00); VREF=2000; break;//1V/div
}
}
//EEPROM功能函数
#define sda_24c64_1XGpio_DiscreteSet(&gpio5,1,1)//24c64定义数据线
#define sda_24c64_0XGpio_DiscreteClear(&gpio5,1,1)//24c64定义数据线
#define scl_24c64_1XGpio_DiscreteSet(&gpio5,1,2)//24c64定义时钟线
#define scl_24c64_0XGpio_DiscreteClear(&gpio5,1,2) //24c64定义时钟线
void start_24c64()
{
sda_24c64_1;
delay_us(1);//后来加上的
scl_24c64_1;
delay_us(20);
sda_24c64_0;
delay_us(20);
scl_24c64_0;
}
void stop_24c64()
{
sda_24c64_0;
delay_us(1);//后来加上的
scl_24c64_1;
delay_us(10);
sda_24c64_1;
delay_us(10);
scl_24c64_0;
}
void ask_24c64() //写数据应答，第九个脉冲sda_24c64为低，则24c64成功接受数据
{
uchar k=30,j;
scl_24c64_0;
delay_us(1);//后来加上的
scl_24c64_1;
delay_us(10);
XGpio_SetDataDirection (&gpio5, 1, 1); //配置成输入
j=(uchar)(XGpio_DiscreteRead (&gpio5, 1)&0x01);
while(j&&k--){j = (uchar)(XGpio_DiscreteRead (&gpio5, 1)&0x01);}//结合写数据发第九个脉冲，检查应答位，若无应答，一定时间后退出
XGpio_SetDataDirection (&gpio5, 1, 0); //配置成输出
scl_24c64_0;
}
void writebyte_24c64(uchar data_to_24c64)
{
uchar i;
scl_24c64_0;
delay_us(1);//后来加上的
for(i=0;i<8;i++)
{
if(data_to_24c64&0x80) sda_24c64_1; else sda_24c64_0;
delay_us(1);//后来加上的
scl_24c64_1; //时钟线低变高，发数据
delay_us(10);
scl_24c64_0;
data_to_24c64<<=1;
}
ask_24c64();
}
uchar readbyte_24c64() //ack应答位，ack=1，MCU不应答（不继续接受数据）
{ //ack=0，MCU应答，继续接受数据
uchar i,data_from_24c64;
scl_24c64_0;
XGpio_SetDataDirection (&gpio5, 1, 1); //配置成输入
for(i=0;i<8;i++)
{
delay_us(1);//后来加上的
data_from_24c64<<=1;
scl_24c64_1;
delay_us(10);
data_from_24c64 |= (uchar)(XGpio_DiscreteRead (&gpio5, 1)&0x01);
delay_us(10);
scl_24c64_0;
}
delay_us(1);//后来加上的
scl_24c64_1;
delay_us(1);//后来加上的
scl_24c64_0;
delay_us(1);//后来加上的
XGpio_SetDataDirection (&gpio5, 1, 0); //配置成输出
sda_24c64_1;
return data_from_24c64;
}
uchar huifang[]=//回放
{
//-文字:回
//--新宋体12;此字体下对应的点阵为：宽x高=16x16
0x00,0x00,0x3F,0xF8,0x20,0x08,0x20,0x08,0x27,0xC8,0x24,0x48,0x24,0x48,0x24,0x48,
0x24,0x48,0x24,0x48,0x27,0xC8,0x20,0x08,0x20,0x08,0x3F,0xF8,0x20,0x08,0x00,0x00,
//--文字:放
//--新宋体12;此字体下对应的点阵为：宽x高=16x16
0x20,0x40,0x10,0x40,0x00,0x40,0xFE,0x80,0x20,0xFE,0x21,0x08,0x3E,0x88,0x24,0x88,
0x24,0x88,0x24,0x50,0x24,0x50,0x24,0x20,0x44,0x50,0x54,0x88,0x89,0x04,0x02,0x02
} ;
void write_ch(uint x,uint y,unsigned char *ch)
{ uint j;
ulong tmp=0,tmpaddr;
unsigned char *temp={ch,ch+1,ch+32,ch+33};
for(j=0;j<16;j++)
{
tmp=0;
tmp|=((unsigned long)(*temp))<<24;
tmp|=((unsigned long)(*temp))<<16;
tmp|=((unsigned long)(*temp))<<8;
tmp|=((unsigned long)(*temp));
tmpaddr=(unsigned long)((y+j)*10+x);
XGpio_DiscreteWrite (&addr12, 1, tmpaddr+4096);
XGpio_DiscreteWrite (&data32, 1, tmp);
temp+=2;temp+=2;temp+=2;temp+=2;
}
} 顶一下 MARK 顶帖的不用活了 还是发工程文件吧 hao niubi 貌似认识LZ，顶一个 mark mark mark 还是发下工程文件吧。 回复【3楼】not_at_all
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ISE的工程文件有点大，压缩包有50M。。学校这个网速不允许阿。。。。。。。 mark mark mark 不管怎么样，先MARK一下！ mark 大牛！ 好长好长。。。 mark mark 很好 好好学习。 不错，赞一个
楼主把*.v *.mhs *.mss和C文件上传就可以了，这样比较小 还是发工程文件吧 mark，赞一个！ 你好！我现在也在做一个FPGA数字存储示波器，看了你的帖子感觉很有帮助，希望你能给我发一下原理图和源代码或者工程文件。不胜感激！谢谢了！
511049445@qq.com 找个时间学习一下! 这这。。。。。。。这样也行 大神啊 先mark下 sdu1028 发表于 2010-11-15 20:21
回复【3楼】not_at_all
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