本人用Verilog写的数码管动态显示测试程序，个人感觉效率极低，不知哪位大虾帮忙看看，可
module shumaguan(rst_n,clk,
SW,sem_cs,sem_db
);
input rst_n,clk;
input SW;
output sem_cs;
output sem_db;
reg sem_cs;
reg sem_db;
parameter
sem_seg_0 = 8'hc0, // "0"
sem_seg_1 = 8'hf9, // "1"
sem_seg_2 = 8'ha4, // "2"
sem_seg_3 = 8'hb0, // "3"
sem_seg_4 = 8'h99, // "4"
sem_seg_5 = 8'h92, // "5"
sem_seg_6 = 8'h82, // "6"
sem_seg_7 = 8'hf8, // "7"
sem_seg_8 = 8'h80, // "8"
sem_seg_9 = 8'h90, // "9"
sem_seg_a = 8'h88, // "a"
sem_seg_b = 8'h83, // "b"
sem_seg_c = 8'hc6, // "c"
sem_seg_d = 8'ha1, // "d"
sem_seg_e = 8'h86, // "e"
sem_seg_f = 8'h8e; // "f"
//reg Data;
reg count1;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
count1 <= 28'h0000000;
end
else if(count1 == 28'd40000000) count1 <= 28'h0000000;
else count1 <= count1 + 1'b1;
end
reg dis;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n) dis <= 4'h0;
else if(dis == 12'd4000) dis <= 12'h000;
else if(count1 == 28'd40000000) dis <= dis + 1'b1;
end
reg ge,shi,bai,qian;
always@(dis)
begin
ge <= dis;
shi <= dis;
bai <= dis;
qian <= 0;
end
reg fresh_cou;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n) fresh_cou <= 24'h000000;
else if(fresh_cou == 24'd200000) fresh_cou <= 24'h000000;
else fresh_cou <= fresh_cou + 1'b1;
end
reg fresh_1;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n) fresh_1 <= 3'd0;
else if(fresh_1 == 3'd4) fresh_1 <= 3'd0;
else if(fresh_cou == 24'd200000)fresh_1 <= fresh_1 + 1'b1;
end
reg dis_data;
always@(dis)
begin
case(fresh_1)
3'b000: begin sem_cs <= 7'b1111110; dis_data <= ge; end
3'b001: begin sem_cs <= 7'b1111101; dis_data <= shi; end
3'b010: begin sem_cs <= 7'b1111011; dis_data <= bai; end
3'b011: begin sem_cs <= 7'b1110111; dis_data <= qian; end
endcase
case(dis_data)
4'h0: sem_db <= sem_seg_0;
4'h1: sem_db <= sem_seg_1;
4'h2: sem_db <= sem_seg_2;
4'h3: sem_db <= sem_seg_3;
4'h4: sem_db <= sem_seg_4;
4'h5: sem_db <= sem_seg_5;
4'h6: sem_db <= sem_seg_6;
4'h7: sem_db <= sem_seg_7;
4'h8: sem_db <= sem_seg_8;
4'h9: sem_db <= sem_seg_9;
4'ha: sem_db <= sem_seg_a;
4'hb: sem_db <= sem_seg_b;
4'hc: sem_db <= sem_seg_c;
4'hd: sem_db <= sem_seg_d;
4'he: sem_db <= sem_seg_e;
4'hf: sem_db <= sem_seg_f;
endcase
end
endmodule http://cache.amobbs.com/bbs_upload782111/files_34/ourdev_595355HV8HD2.jpg
逻辑块使用情况，竟然高达64%！ (原文件名:1.jpg) 还有就是，不知道用Verilog如何将16进制数转为10进制数啊！ 是太大了点
我的占用了大概30%左右 回复【2楼】hdd961140543
还有就是，不知道用verilog如何将16进制数转为10进制数啊！
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其实你不用16进制计数就好了
各位分别计数就不用转换进制了，只多几条语句，应该比进制转换更简单 哦，这样啊，多谢了，我试试看 epm240基本做不了多少事。只能用来做点简单的东西。 我是一个初学者，刚开始学Verilog。 如果单纯计数器显示,用BCD计数比较方便,如果其他场合要把BIN转BCD,参考我这贴
http://www.ourdev.cn/bbs/bbs_content.jsp?bbs_sn=4215535&bbs_page_no=1&search_mode=3&search_text=888888888888&bbs_id=9999 http://blog.ednchina.com/akuei2/1722910/message.aspx
http://cid-c8c65500aea2fb15.office.live.com/self.aspx/Verilog%20HDL%20那些事儿%20（继续未完的故事%20）/第三章1.rar
http://cid-c8c65500aea2fb15.office.live.com/self.aspx/Verilog%20HDL%20那些事儿%20（继续未完的故事%20）/第五章2.rar 用function函数转换啊，输入十进制，对应输出数码管数值
//function : convert number to led-formed data
function data_convert;
input data;
reg led;
case( data )
4'd0: led = ~7'h3f; //0
4'd1: led = ~7'h06; //1
4'd2: led = ~7'h5b; //2
4'd3: led = ~7'h4f; //3
4'd4: led = ~7'h66; //4
4'd5: led = ~7'h6d; //5
4'd6: led = ~7'h7d; //6
4'd7: led = ~7'h07; //7
4'd8: led = ~7'h7f; //8
4'd9: led = ~7'h6f; //9
default: led = ~7'h00;
endcase
data_convert = led;
endfunction 对应返回的就是数码管的数据，每次调用就行了 LZ 居然用拼音 不好不好啊 parameter
sem_seg_0 = 8'hc0, // "0"
sem_seg_1 = 8'hf9, // "1"
sem_seg_2 = 8'ha4, // "2"
sem_seg_3 = 8'hb0, // "3"
sem_seg_4 = 8'h99, // "4"
sem_seg_5 = 8'h92, // "5"
sem_seg_6 = 8'h82, // "6"
sem_seg_7 = 8'hf8, // "7"
sem_seg_8 = 8'h80, // "8"
sem_seg_9 = 8'h90, // "9"
sem_seg_a = 8'h88, // "a"
sem_seg_b = 8'h83, // "b"
sem_seg_c = 8'hc6, // "c"
sem_seg_d = 8'ha1, // "d"
sem_seg_e = 8'h86, // "e"
sem_seg_f = 8'h8e; // "f"
case(dis_data)
4'h0: sem_db <= sem_seg_0;
4'h1: sem_db <= sem_seg_1;
4'h2: sem_db <= sem_seg_2;
4'h3: sem_db <= sem_seg_3;
4'h4: sem_db <= sem_seg_4;
4'h5: sem_db <= sem_seg_5;
4'h6: sem_db <= sem_seg_6;
4'h7: sem_db <= sem_seg_7;
4'h8: sem_db <= sem_seg_8;
4'h9: sem_db <= sem_seg_9;
4'ha: sem_db <= sem_seg_a;
4'hb: sem_db <= sem_seg_b;
4'hc: sem_db <= sem_seg_c;
4'hd: sem_db <= sem_seg_d;
4'he: sem_db <= sem_seg_e;
4'hf: sem_db <= sem_seg_f;
endcase
end
你这个表会占用一大堆D flip-flop 也就是一大堆 逻辑单元
建议用逻辑门实现BCD到七段的译码 这才是CPLD的长项 回复【13楼】YFM_LMM
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多谢YFM_LMM的提醒！ 回复【10楼】leilei2268967
//function : convert number to led-formed data
function data_convert;
input data;
reg led;
case( data )
4'd0: led = ~7'h3f; //0
4'd1: led = ~7'h06; //1
4'd2: led = ~7'h5b; //2
4'd3: led = ~7'h4f; //3
4'd4: led = ~7'h66; //4
4'd5: led = ~7'h6d; //5
4'd6: led = ~7'h7d; //6
4'd7: led = ~7'h07; //7
4'd8: led = ~7'h7f; //8
4'd9: led = ~7'h6f; //9
default: led = ~7'h00;
endcase
data_convert = led;
endfunction
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这种方式很不错啊！ 记号 回复【15楼】hdd961140543阿逸
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组合逻辑多用阻塞赋值“=”
时序逻辑多用非阻塞赋值“<=”
综合后还是有差异的 看来如何优化也是一种学问
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