请教用MDK4.12调试S3C2440 的时钟速度问题
刚开始学习使用MDK4.12 将原来在ADS上使用的lcd驱动移植过来，用的是MDK自带的启动代码，不知为什么时钟速度提不上去，一开始以为是快速总线没改成异步总线 ，回来修改了启动代码，还是不行，求高手指点启动代码如下：
;/*****************************************************************************/
;/* S3C2440A.S: Startup file for Samsung S3C440A */
;/*****************************************************************************/
;/* <<< Use Configuration Wizard in Context Menu >>> */
;/*****************************************************************************/
;/* This file is part of the uVision/ARM development tools. */
;/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */
;/* This software may only be used under the terms of a valid, current, */
;/* end user licence from KEIL for a compatible version of KEIL software */
;/* development tools. Nothing else gives you the right to use this software. */
;/*****************************************************************************/
; *** Startup Code (executed after Reset) ***
; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
Mode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UND EQU 0x1B
Mode_SYS EQU 0x1F
I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
;// <h> Stack Configuration (Stack Sizes in Bytes)
;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8>
;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8>
;// <o2> Abort Mode <0x0-0xFFFFFFFF:8>
;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8>
;// <o5> User/System Mode <0x0-0xFFFFFFFF:8>
;// </h>
UND_Stack_SizeEQU 0x00000000
SVC_Stack_SizeEQU 0x00000008
ABT_Stack_SizeEQU 0x00000000
FIQ_Stack_SizeEQU 0x00000000
IRQ_Stack_SizeEQU 0x00000080
USR_Stack_SizeEQU 0x00000400
ISR_Stack_SizeEQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
FIQ_Stack_Size + IRQ_Stack_Size)
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE USR_Stack_Size
__initial_sp SPACE ISR_Stack_Size
Stack_Top EQU Stack_Mem + ISR_Stack_Size
;// <h> Heap Configuration
;// <o>Heap Size (in Bytes) <0x0-0xFFFFFFFF>
;// </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
Heap_Mem SPACE Heap_Size
; Clock Management definitions
CLK_BASE EQU 0x4C000000 ; Clock Base Address
LOCKTIME_OFS EQU 0x00 ; LOCKTIME Offset
MPLLCON_OFS EQU 0x04 ; MPLLCON Offset
UPLLCON_OFS EQU 0X08 ; UPLLCON Offset
CLKCON_OFS EQU 0x0C ; CLKCON Offset
CLKSLOW_OFS EQU 0x10 ; CLKSLOW Offset
CLKDIVN_OFS EQU 0X14 ; CLDKIVN Offset
CAMDIVN_OFS EQU 0X18 ; CAMDIVN Offset
CLOCK_SETUP EQU 1
LOCKTIME_Val EQU 0x0FFF0FFF
MPLLCON_Val EQU 0x0005C011
UPLLCON_Val EQU 0x0003A021
CLKCON_Val EQU 0x00FFFFF0
CLKSLOW_Val EQU 0x00000004
CLKDIVN_Val EQU 0x00000005
CAMDIVN_Val EQU 0x00000000
;Interruptdefinitions
INTOFFSET EQU 0X4A000014 ;Address of Interrupt offset Register
;//<e> Interrupt Vector Table
;//<o1.0..31> Interrupt Vector address <0x20-0x3fffff78>
;// <i> You could define Interuupt Vctor Table address.
;// <i> The Interrupt Vector Table address must be word aligned adress.
;//</e>
IntVT_SETUP EQU 1
IntVTAddress EQU 0x33ffff20
INTMSK EQU 0x4A000008
INTSUBMSK EQU 0x4A00001C
;----------------------- Memory Definitions ------------------------------------
; Internal Memory Base Addresses
IRAM_BASE EQU 0x40000000
; Watchdog Timer definitions
WT_BASE EQU 0x53000000 ; WT Base Address
WTCON_OFS EQU 0x00 ; WTCON Offset
WTDAT_OFS EQU 0x04 ; WTDAT Offset
WTCNT_OFS EQU 0x08 ; WTCNT Offset
;// <e> Watchdog Timer
;// <o1.5> Watchdog Timer Enable/Disable
;// <o1.0> Reset Enable/Disable
;// <o1.2> Interrupt Enable/Disable
;// <o1.3..4> Clock Select
;// <0=> 1/16<1=> 1/32<2=> 1/64<3=> 1/128
;// <i> Clock Division Factor
;// <o1.8..15>Prescaler Value <0x0-0xFF>
;// <o2.0..15>Time-out Value<0x0-0xFFFF>
;// </e>
WT_SETUP EQU 1
WTCON_Val EQU 0x00000000
WTDAT_Val EQU 0x00008000
; Memory Controller definitions
MC_BASE EQU 0x48000000 ; Memory Controller Base Address
;// <e> Memory Controller
MC_SETUP EQU 0
BWSCON_Val EQU 0x22000000
BANKCON0_Val EQU 0x00000700
BANKCON1_Val EQU 0x00000700
BANKCON2_Val EQU 0x00000700
BANKCON3_Val EQU 0x00000700
BANKCON4_Val EQU 0x00000700
BANKCON5_Val EQU 0x00000700
BANKCON6_Val EQU 0x00018005
BANKCON7_Val EQU 0x00018005
REFRESH_Val EQU 0x008404F3
BANKSIZE_Val EQU 0x00000032
MRSRB6_Val EQU 0x00000020
MRSRB7_Val EQU 0x00000020
;// </e> End of MC
; I/O Ports definitions
PIO_BASE EQU 0x56000000 ; PIO Base Address
PCONA_OFS EQU 0x00 ; PCONA Offset
PCONB_OFS EQU 0x10 ; PCONB Offset
PCONC_OFS EQU 0x20 ; PCONC Offset
PCOND_OFS EQU 0x30 ; PCOND Offset
PCONE_OFS EQU 0x40 ; PCONE Offset
PCONF_OFS EQU 0x50 ; PCONF Offset
PCONG_OFS EQU 0x60 ; PCONG Offset
PCONH_OFS EQU 0x70 ; PCONH Offset
PCONJ_OFS EQU 0xD0 ; PCONJ Offset
PUPB_OFS EQU 0x18 ; PUPB Offset
PUPC_OFS EQU 0x28 ; PUPC Offset
PUPD_OFS EQU 0x38 ; PUPD Offset
PUPE_OFS EQU 0x48 ; PUPE Offset
PUPF_OFS EQU 0x58 ; PUPF Offset
PUPG_OFS EQU 0x68 ; PUPG Offset
PUPH_OFS EQU 0x78 ; PUPH Offset
PUPJ_OFS EQU 0xD8 ; PUPJ Offset
;// <e> I/O Configuration
PIO_SETUP EQU 0
;// <e> Port A
;// <o1.0> PA0<0=> Output <1=> ADDR0
;// <o1.1> PA1<0=> Output <1=> ADDR16
;// <o1.2> PA2<0=> Output <1=> ADDR17
;// </e>
PIOA_SETUP EQU 0
PCONA_Val EQU 0x000003FF
;// </h>
;// </e>
PIOB_SETUP EQU 0
PCONB_Val EQU 0x00000000
PUPB_Val EQU 0x00000000
;// </h>
;// </e>
PIOC_SETUP EQU 1
PCONC_Val EQU 0x00001401
PUPC_Val EQU 0x00000000
;// </h>
;// </e>
PIOD_SETUP EQU 0
PCOND_Val EQU 0x00000000
PUPD_Val EQU 0x00000000
;// </h>
;// </e>
PIOE_SETUP EQU 0
PCONE_Val EQU 0x00000000
PUPE_Val EQU 0x00000000
;// <e> Port F
;// <o1.0..1> PF0<0=> Input <1=> Output<2=> EINT<3=> Reserved
;// <o1.2..3> PF1<0=> Input <1=> Output<2=> EINT<3=> Reserved
;// <o1.4..5> PF2<0=> Input <1=> Output<2=> EINT<3=> Reserved
;// <o1.6..7> PF3<0=> Input <1=> Output<2=> EINT<3=> Reserved
;// <o1.8..9> PF4<0=> Input <1=> Output<2=> EINT<3=> Reserved
;// <o1.10..11> PF5<0=> Input <1=> Output<2=> EINT<3=> Reserved
;// <o1.12..13> PF6<0=> Input <1=> Output<2=> EINT<3=> Reserved
;// <o1.14..15> PF7<0=> Input <1=> Output<2=> EINT<3=> Reserved
;// <h> Pull-up Resistors
;// <o2.0> PF0 Pull-up <0=> Enabled<1=> Disabled
;// <o2.1> PF1 Pull-up <0=> Enabled<1=> Disabled
;// <o2.2> PF2 Pull-up <0=> Enabled<1=> Disabled
;// <o2.3> PF3 Pull-up <0=> Enabled<1=> Disabled
;// <o2.4> PF4 Pull-up <0=> Enabled<1=> Disabled
;// <o2.5> PF5 Pull-up <0=> Enabled<1=> Disabled
;// <o2.6> PF6 Pull-up <0=> Enabled<1=> Disabled
;// <o2.7> PF7 Pull-up <0=> Enabled<1=> Disabled
;// </h>
;// </e>
PIOF_SETUP EQU 0
PCONF_Val EQU 0x00000000
PUPF_Val EQU 0x00000000
;// </e>
PIOG_SETUP EQU 0
PCONG_Val EQU 0x00000000
PUPG_Val EQU 0x00000000
;// </h>
;// </e>
PIOH_SETUP EQU 0
PCONH_Val EQU 0x000007FF
PUPH_Val EQU 0x00000000
;// </h>
;// </e>
PIOJ_SETUP EQU 0
PCONJ_Val EQU 0x00000000
PUPJ_Val EQU 0x00000000
PRESERVE8
; Area Definition and Entry Point
;Startup Code must be linked first at Address at which it expects to run.
AREA RESET, CODE, READONLY
ARM
; Exception Vectors
;Mapped to Address 0.
;Absolute addressing mode must be used.
;Dummy Handlers are implemented as infinite loops which can be modified.
Vectors LDR PC, Reset_Addr
LDR PC, Undef_Addr
LDR PC, SWI_Addr
LDR PC, PAbt_Addr
LDR PC, DAbt_Addr
NOP ; Reserved Vector
LDR PC, IRQ_Addr
LDR PC, FIQ_Addr
IF IntVT_SETUP <> 0
;Interrupt Vector Table Address
HandleEINT0 EQU IntVTAddress
HandleEINT1 EQU IntVTAddress +4
HandleEINT2 EQU IntVTAddress +4*2
HandleEINT3 EQU IntVTAddress +4*3
HandleEINT4_7 EQU IntVTAddress +4*4
HandleEINT8_23 EQU IntVTAddress +4*5
HandleCAM EQU IntVTAddress +4*6
HandleBATFLT EQU IntVTAddress +4*7
HandleTICK EQU IntVTAddress +4*8
HandleWDT EQU IntVTAddress +4*9
HandleTIMER0 EQU IntVTAddress +4*10
HandleTIMER1 EQU IntVTAddress +4*11
HandleTIMER2 EQU IntVTAddress +4*12
HandleTIMER3 EQU IntVTAddress +4*13
HandleTIMER4 EQU IntVTAddress +4*14
HandleUART2 EQU IntVTAddress +4*15
HandleLCD EQU IntVTAddress +4*16
HandleDMA0 EQU IntVTAddress +4*17
HandleDMA1 EQU IntVTAddress +4*18
HandleDMA2 EQU IntVTAddress +4*19
HandleDMA3 EQU IntVTAddress +4*20
HandleMMC EQU IntVTAddress +4*21
HandleSPI0 EQU IntVTAddress +4*22
HandleUART1 EQU IntVTAddress +4*23
HandleNFCON EQU IntVTAddress +4*24
HandleUSBD EQU IntVTAddress +4*25
HandleUSBH EQU IntVTAddress +4*26
HandleIIC EQU IntVTAddress +4*27
HandleUART0 EQU IntVTAddress +4*28
HandleSPI1 EQU IntVTAddress +4*39
HandleRTC EQU IntVTAddress +4*30
HandleADC EQU IntVTAddress +4*31
IRQ_Entry
sub sp,sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r9,=INTOFFSET
ldr r9,
ldr r8,=HandleEINT0
add r8,r8,r9,lsl #2
ldr r8,
str r8,
ldmfd sp!,{r8-r9,pc}
ENDIF
Reset_Addr DCD Reset_Handler
Undef_Addr DCD Undef_Handler
SWI_Addr DCD SWI_Handler
PAbt_Addr DCD PAbt_Handler
DAbt_Addr DCD DAbt_Handler
DCD 0 ; Reserved Address
IRQ_Addr DCD IRQ_Handler
FIQ_Addr DCD FIQ_Handler
Undef_Handler B Undef_Handler
SWI_Handler B SWI_Handler
PAbt_Handler B PAbt_Handler
DAbt_Handler B DAbt_Handler
IF IntVT_SETUP <> 1
IRQ_Handler B IRQ_Handler
ENDIF
IF IntVT_SETUP <> 0
IRQ_Handler B IRQ_Entry
ENDIF
FIQ_Handler B FIQ_Handler
; Memory Controller Configuration
IF MC_SETUP <> 0
MC_CFG
DCD BWSCON_Val
DCD BANKCON0_Val
DCD BANKCON1_Val
DCD BANKCON2_Val
DCD BANKCON3_Val
DCD BANKCON4_Val
DCD BANKCON5_Val
DCD BANKCON6_Val
DCD BANKCON7_Val
DCD REFRESH_Val
DCD BANKSIZE_Val
DCD MRSRB6_Val
DCD MRSRB7_Val
ENDIF
; Clock Management Configuration
IF CLOCK_SETUP <> 0
CLK_CFG
DCD LOCKTIME_Val
DCD CLKDIVN_Val
DCD UPLLCON_Val
DCD MPLLCON_Val
DCD CLKSLOW_Val
DCD CLKCON_Val
DCD CAMDIVN_Val
ENDIF
; I/O Configuration
IF PIO_SETUP <> 0
PIOA_CFG
DCD PCONA_Val
PIOB_CFG DCD PCONB_Val
DCD PUPB_Val
PIOC_CFG DCD PCONC_Val
DCD PUPC_Val
PIOD_CFG DCD PCOND_Val
DCD PUPD_Val
PIOE_CFG DCD PCONE_Val
DCD PUPE_Val
PIOF_CFG DCD PCONF_Val
DCD PUPF_Val
PIOG_CFG DCD PCONG_Val
DCD PUPG_Val
PIOH_CFG DCD PCONH_Val
DCD PUPH_Val
PIOJ_CFG DCD PCONJ_Val
DCD PUPJ_Val
ENDIF
; Reset Handler
EXPORTReset_Handler
Reset_Handler
IF WT_SETUP <> 0
LDR R0, =WT_BASE
LDR R1, =WTCON_Val
LDR R2, =WTDAT_Val
STR R2,
STR R2,
STR R1,
ENDIF
IF CLOCK_SETUP <> 0
LDR R0, =CLK_BASE
ADR R8, CLK_CFG
LDMIA R8, {R1-R7}
STR R1,
STR R2,
mrc p15,0,r0,c1,c0,0 //自己添加的总线模式切换
orr r0,r0,#0xc0000000;R1_nF:OR:R1_iA
mcr p15,0,r0,c1,c0,0
STR R3,
nop
nop
nop
nop
nop
nop
nop
STR R4,
STR R5,
STR R6,
STR R7,
ENDIF
IF MC_SETUP <> 0
ADR R13, MC_CFG
LDMIA R13, {R0-R12}
LDR R13, =MC_BASE
STMIA R13, {R0-R12}
ENDIF
IF PIO_SETUP <> 0
LDR R13, =PIO_BASE
IF PIOA_SETUP <> 0
ADR R0, PIOA_CFG
STR R0,
ENDIF
IF PIOB_SETUP <> 0
ADR R0, PIOB_CFG
LDR R1,
STR R0,
STR R1,
ENDIF
IF PIOC_SETUP <> 0
ADR R0, PIOC_CFG
LDR R1,
STR R0,
STR R1,
ENDIF
IF PIOD_SETUP <> 0
ADR R0, PIOD_CFG
LDR R1,
STR R0,
STR R1,
ENDIF
IF PIOE_SETUP <> 0
ADR R0, PIOE_CFG
LDR R1,
STR R0,
STR R1,
ENDIF
IF PIOF_SETUP <> 0
ADR R0, PIOF_CFG
LDR R1,
STR R0,
STR R1,
ENDIF
IF PIOG_SETUP <> 0
ADR R0, PIOG_CFG
LDR R1,
STR R0,
STR R1,
ENDIF
IF PIOH_SETUP <> 0
ADR R0, PIOH_CFG
LDR R1,
STR R0,
STR R1,
ENDIF
IF PIOJ_SETUP <> 0
ADR R0, PIOJ_CFG
LDR R1,
STR R0,
STR R1,
ENDIF
ENDIF
; Setup Stack for each mode
LDR R0, =Stack_Top
;Enter Undefined Instruction Mode and set its Stack Pointer
MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #UND_Stack_Size
;Enter Abort Mode and set its Stack Pointer
MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #ABT_Stack_Size
;Enter FIQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #FIQ_Stack_Size
;Enter IRQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #IRQ_Stack_Size
;Enter Supervisor Mode and set its Stack Pointer
MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #SVC_Stack_Size
; IMPORT MMU_EnableICache
; bl MMU_EnableICache
;Enter User Mode and set its Stack Pointer
MSR CPSR_c, #Mode_USR
MOV SP, R0
SUB SL, SP, #USR_Stack_Size
; Enter the C code
;
IMPORT__main
LDR R0, =__main
BX R0
; User Initial Stack & Heap
AREA |.text|, CODE, READONLY
; IMPORT__use_two_region_memory
EXPORT__user_initial_stackheap
__user_initial_stackheap
LDR R0, =Heap_Mem
LDR R1, =(Stack_Mem + USR_Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
END
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