Modelsim仿真时提示：'i2' already declared in this scope
原文是：# ** Error: D:/FPGA_test2/simulation/modelsim/MUX.vt(27): 'i2' already declared in this scope.
# ** Error: D:/software/modeltech_6.5/win32/vlog failed.
我刚接触FPGA，连verilog都没掌握好，实在找不到哪里出错。我把程序改得相当简单，依然提示以上错误。究竟是什么问题？请各位指教。
.v程序如下：
module MUX(i0,i1,i2,i3,s1,s0,out);
input i0;
input i1;
input i2;
input i3;
input s1;
input s0;
output out;
assign out=1;
endmodule
.vt程序如下：
`timescale 1 ns/ 1 ns
module MUX_vlg_tst();
reg eachvec;
reg i0;
reg i1;
reg i2;
reg i3;
reg s0;
reg s1;
wire out;
MUX i2 (
.i0(i0),
.i1(i1),
.i2(i2),
.i3(i3),
.out(out),
.s0(s0),
.s1(s1)
);
assign out=1;
endmodule
页:
[1]