请教关于使用DSP builder出现的一个错误
Error: IP Generator Error: Entity 'alt_dspbuilder_clock' (Version latest) not found in librarian.Info: Found 1 design units, including 1 entities, in source file ../am_mod.mdl
Info: Found entity 1: am_mod_Interface
Error: Top-level design entity "am_mod" is undefined
Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings
Error: Peak virtual memory: 155 megabytes
Error: Processing ended: Thu Sep 02 16:38:50 2010
Error: Elapsed time: 00:00:09
Error: Total CPU time (on all processors): 00:00:01
Error: Error during compilation: Synthesis failed
用DSP Builder compiler 成HDL时候 出现的错误，不知道原因，百度的结果是说 把什么 ip_cache 删除，可是 这个文件夹根本找不到，请教 大家，这个是什么问题啊 已经找到。。。我真笨，，，，PS 还有一个问题 请问DSP builder可以生成Verilog 描述吗
页:
[1]