请教一个关于SRAM读写与串口发送程序的问题 verilog hdl语言
// SRAMclt.vmodule SRAMclt(clk,reset,data_inout,Addr,nCE,nWE,nOE,nUB,nLB,TXD);
input clk,reset;//时钟，复位
inout data_inout;//SRAM数据输入输出
output Addr;//SRAM地址输出
output nCE,nWE,nOE,nUB,nLB;//nCE片选,nWE写使能，nOE读使能，nUB高8位数据使能，nLB低8位数据使能
output TXD;//串口通讯
reg data_high;
reg data_low;
reg regdata;
reg readdata;
reg Addr;
reg nWE,nOE;
wire nCE,nUB,nLB;
reg regTXD;
reg bincnt;
reg sendbuff;
reg sendbuff_low;
reg sendbuff_high;
reg state;
reg cnt;
wire clk_equ;
parameter init_mode = 6'b000000;
parameter write_SRAM = 6'b000001;
parameter Addr_add = 6'b000010;
parameter read_mode = 6'b000011;
parameter Add_Addr = 6'b000100;
parameter read_data = 6'b000101;
parameter send_ready = 6'b000110;
parameter send_data_low = 6'b000111;
parameter send_data_high = 6'b001000;
parameter send_over = 6'b001001;
assign nCE = 1'b0;
assign nUB = 1'b0;
assign nLB = 1'b0;
assign data_inout = regdata;
assign TXD = regTXD;
/*****波特率产生*******/
always@(posedge clk)
begin
if(reset) cnt <= 8'd0;
else
begin
if(clk_equ) cnt <= 8'd0;
else cnt <= cnt + 1'b1;
end//else
end//always
assign clk_equ = (cnt==5000);
always@(posedge clk)
begin
if(reset)
begin
state <= init_mode;
end//if(reset)
else
begin
case(state)
init_mode:
begin
nWE <= 1'b0;
nOE <= 1'b1;
regdata <= 16'd0;
Addr <= 18'd0;
data_low <= 8'd0;
data_high <= 8'd0;
state <= write_SRAM;
end
write_SRAM:
begin
nOE <= 1'b1;
regdata <= {data_high,data_low};
state <= Addr_add;
end
Addr_add:
begin
Addr <= Addr + 1'b1;
data_low <= data_low + 1'b1;
data_high <= data_high + 1'b1;
if(Addr==8'd255)
begin
nWE <= 1'b1;
nOE <= 1'b0;
Addr <= 18'd0;
regdata <= 16'hzz;
state <= read_mode;
end
else
begin
state <= write_SRAM;
end
end
read_mode:
begin
readdata <= data_inout;
state <= Add_Addr;
end
Add_Addr:
begin
Addr <= Addr + 1'b1;
if(Addr==8'd255)
begin
nWE <= 1'b1;
nOE <= 1'b1;
Addr <= 18'd0;
state <= send_over;
end
else
begin
state <= read_data;
end
end
read_data:
begin
data_low <= readdata;
data_high <= (readdata>>8);
state <= send_ready;
end
send_ready:
begin
sendbuff_low <= {1'b1,data_low,1'b0};
sendbuff_high <= {1'b1,data_high,1'b0};
sendbuff <= 10'd0;
bincnt <= 4'd0;
state <= send_data_low;
end
send_data_low:
begin
if(clk_equ)
begin
if(bincnt<4'd10)
begin
regTXD <= sendbuff;
sendbuff <= (sendbuff_low>>bincnt);
bincnt <= bincnt + 4'd1;
state <= send_data_low;
end
else
begin
regTXD <= 1'b1;
bincnt <= 4'd0;
sendbuff <= 10'd0;
state <= send_data_high;
end
end
else
begin
state <= send_data_low;
end
end
send_data_high:
begin
if(clk_equ)
begin
if(bincnt<4'd10)
begin
regTXD <= sendbuff;
sendbuff <= (sendbuff_high>>bincnt);
bincnt <= bincnt + 4'd1;
state <= send_data_high;
end
else
begin
regTXD <= 1'b1;
bincnt <= 4'd0;
state <= read_mode;
end
end
else
begin
state <= send_data_high;
end
end
send_over:
begin
state <= send_over;
end
default: state <= init_mode;
endcase
end//else
end//always
endmodule
我本想写0至FF到SRAM然后读出发送到串口。那串口接收的数据应该是:00 00 01 01 02 02 03 03 04 04 ........
但是出乎意料的是，串口真正接收到的是：
00 00 02 02 04 04 06 06 08 08 0A 0A 0C 0C 0E 0E 10 10 12 12 14 14 16 16 18 18 1A 1A 1C 1C 1E 1E 20 20 22 22 24 24 26 26 28 28 2A 2A 2C 2C 2E 2E 30 30 32 32 34 34 36 36 38 38 3A 3A 3C 3C 3E 3E 40 40 42 42 44 44 46 46 48 48 4A 4A 4C 4C 4E 4E 50 50 52 52 54 54 56 56 58 58 5A 5A 5C 5C 5E 5E 60 60 62 62 64 64 66 66 68 68 6A 6A 6C 6C 6E 6E 70 70 72 72 74 74 76 76 78 78 7A 7A 7C 7C 7E 7E 80 80 82 82 84 84 86 86 88 88 8A 8A 8C 8C 8E 8E 90 90 92 92 94 94 96 96 98 98 9A 9A 9C 9C 9E 9E A0 A0 A2 A2 A4 A4 A6 A6 A8 A8 AA AA AC AC AE AE B0 B0 B2 B2 B4 B4 B6 B6 B8 B8 BA BA BC BC BE BE C0 C0 C2 C2 C4 C4 C6 C6 C8 C8 CA CA CC CC CE CE D0 D0 D2 D2 D4 D4 D6 D6 D8 D8 DA DA DC DC DE DE E0 E0 E2 E2 E4 E4 E6 E6 E8 E8 EA EA EC EC EE EE F0 F0 F2 F2 F4 F4 F6 F6 F8 F8 FA FA FC FC FE FE 00 00 02 02 04 04 06 06 08 08 0A 0A 0C 0C 0E 0E 10 10 12 12 14 14 16 16 18 18 1A 1A 1C 1C 1E 1E 20 20 22 22 24 24 26 26 28 28 2A 2A 2C 2C 2E 2E 30 30 32 32 34 34 36 36 38 38 3A 3A 3C 3C 3E 3E 40 40 42 42 44 44 46 46 48 48 4A 4A 4C 4C 4E 4E 50 50 52 52 54 54 56 56 58 58 5A 5A 5C 5C 5E 5E 60 60 62 62 64 64 66 66 68 68 6A 6A 6C 6C 6E 6E 70 70 72 72 74 74 76 76 78 78 7A 7A 7C 7C 7E 7E 80 80 82 82 84 84 86 86 88 88 8A 8A 8C 8C 8E 8E 90 90 92 92 94 94 96 96 98 98 9A 9A 9C 9C 9E 9E A0 A0 A2 A2 A4 A4 A6 A6 A8 A8 AA AA AC AC AE AE B0 B0 B2 B2 B4 B4 B6 B6 B8 B8 BA BA BC BC BE BE C0 C0 C2 C2 C4 C4 C6 C6 C8 C8 CA CA CC CC CE CE D0 D0 D2 D2 D4 D4 D6 D6 D8 D8 DA DA DC DC DE DE E0 E0 E2 E2 E4 E4 E6 E6 E8 E8 EA EA EC EC EE EE F0 F0 F2 F2 F4 F4 F6 F6 F8 F8 FA FA FC FC
为什么呢？哪位DX帮忙看一下，谢谢！
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