有个网友要的BIN转BCD示范代码,原创(代码原创思路参考前人的)
LIBRARY ieee;USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY UNTITLED IS
PORT (CLK,RESET: IN std_logic;
BIN:buffer std_logic_vector(15 downto 0);
BCD:out std_logic_vector(19 downto 0));
END;
ARCHITECTURE BEHAVIOR OF UNTITLED IS
signal btemp:std_logic_vector(19 downto 0);
signal count:integer range 0 to 31;
BEGIN
PROCESS (CLK,RESET)
variable bt:std_logic_vector(19 downto 0);
BEGIN
IF ( RESET='1' ) THEN
BCD<="00000000000000000000";
btemp<="00000000000000000000";
--BIN<="1001001000010110"; --9216=37398
BIN<="1111111111111111"; --FFFF=65535
count<=0;
ELSIF rising_edge(CLK) THEN
if count<15 then
count<=count+1;
bt:=btemp(18 downto 0)&BIN(15);
BIN(15 downto 1)<=BIN(14 downto 0);
if bt(19 downto 16)>"0100" then
bt(19 downto 16):=bt(19 downto 16)+"0011";
end if;
if bt(15 downto 12)>"0100" then
bt(15 downto 12):=bt(15 downto 12)+"0011";
end if;
if bt(11 downto 8)>"0100" then
bt(11 downto 8):=bt(11 downto 8)+"0011";
end if;
if bt(7 downto 4)>"0100" then
bt(7 downto 4):=bt(7 downto 4)+"0011";
end if;
if bt(3 downto 0)>"0100" then
bt(3 downto 0):=bt(3 downto 0)+"0011";
end if;
elsif count=15 then
count<=count+1;
bt:=btemp(18 downto 0)&BIN(15);
BIN(15 downto 1)<=BIN(14 downto 0);
else
null;
end if;
BCD<=bt;
btemp<=bt;
END IF;
END PROCESS;
END BEHAVIOR; 学习 收了备用 VHDL的啊,不懂哦! 谢谢! 回复【楼主位】888888888888
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求verilog 回复【楼主位】NJ8888
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楼主把BIN作为BUFFER 那怎么调用不是输入了
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