下了个除法器VERILOG 除法器 有点点没懂。
这个程序它在一直不停的算，能不能帮我改下下，只要除数和被除数不变，商和余数算好之后程序就停下。（程序没看懂哈，不然就自己改了）http://cache.amobbs.com/bbs_upload782111/files_32/ourdev_573135.jpg
(原文件名:未命名.jpg)
module divider(quotient,remainder,ready,error,word1,word2,start,clock,reset);
parameter L_divn=8,
L_divr=4,
S_idle=0,S_adivr=1,S_adivn=2,S_div=3,S_err=4,
L_state=3,L_cnt=4,Max_cnt=L_divn-L_divr;
output quotient,remainder;
output ready,error;
input word1;//dividend
input word2;//divisor
input start,clock,reset;//0,start,1,reset
reg state,next_state;
reg Load_words,Subtract,Shift_dividend,Shift_divisor;
reg quotient;
reg dividend;
reg divisor;
reg num_Shift_dividend,num_Shift_divisor;
reg comparison;
wire MSB_divr=divisor;
wire ready=((state==S_idle)&&reset);
wire error=(state==S_err);
wire Max=(num_Shift_dividend==Max_cnt+num_Shift_divisor);
wire sign_bit=comparison;
assignremainder=(dividend)>num_Shift_divisor;/////////
always @(state or dividend or divisor or MSB_divr)
case(state)
S_adivr: if(MSB_divr==0)
comparison=dividend+{1'b1,~(divisor<<1)}+1'b1;
else
comparison=dividend+{1'b1,~divisor}+1'b1;
default: comparison=dividend+{1'b1,~divisor}+1'b1;
endcase
always @(posedge clock or negedge reset)
if(!reset) state<=S_idle; else state<=next_state;
always @(state or word1 or word2 or start or comparison or sign_bit or Max)
begin
Load_words=0;Subtract=0;Shift_dividend=0;Shift_divisor=0;
case(state)
S_idle: case(!start)
0:next_state=S_idle;
1:if(word2==0) next_state=S_err;
else if(word1) begin next_state=S_adivr;Load_words=1; end
else next_state=S_idle;
endcase
S_adivr: case(MSB_divr)
0:if(sign_bit==0) begin next_state=S_adivr;Shift_divisor=1; end
else if(sign_bit==1) next_state=S_adivn;
1:next_state=S_div;
endcase
S_adivn: case({Max,sign_bit})
2'b00:next_state=S_div;
2'b01:begin next_state=S_adivn;Shift_dividend=1; end
2'b10:begin next_state=S_idle;Subtract=1; end
2'b11:next_state=S_idle;
endcase
S_div: case({Max,sign_bit})
2'b00:begin next_state=S_div;Subtract=1; end
2'b01:next_state=S_adivn;
2'b10:begin next_state=S_div;Subtract=1; end
2'b11:begin next_state=S_div;Shift_dividend=1; end
endcase
default: next_state=S_err;
endcase
end
always @(posedge clock or negedge reset)
begin
if(!reset)
begin
divisor<=0;
dividend<=0;
quotient<=0;
num_Shift_dividend<=0;
num_Shift_divisor<=0;
end
else if(Load_words==1)
begin
dividend<=word1;
divisor<=word2;
quotient<=0;
num_Shift_dividend<=0;
num_Shift_divisor<=0;
end
else if(Shift_divisor)
begin
divisor<=divisor<<1;
num_Shift_divisor<=num_Shift_divisor+1;
end
else if(Shift_dividend)
begin
dividend<=dividend<<1;
quotient<=quotient<<1;
num_Shift_dividend<=num_Shift_dividend+1;
end
else if(Subtract)
begin
dividend<=comparison;
quotient<=1;
end
end
endmodule 哎~这个问题我也蛋疼过~
最后倾向IP了~变懒了
啊哈哈！
楼主还是善用资源吧，啊哈哈
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