verilog 一个简单的串口程序，编译通不过
module light(clock, rxd, ledout);input clock;
inputrxd;
output ledout;
reg count_reg;
reg t_b;
reg t;
reg bit_cnt;
reg bit_collect;
reg clock_div;
reg clock_pluse;
reg rxd_start_reg;
reg rxd_end;
//------------------------
always @(posedge clock)
begin
if(clock_div < 8'd250 )//5次机会.
begin
clock_div=clock_div+1;
clock_pluse = 0;
end
else
clock_div = 0;
clock_pluse = 1;
begin
end
end
always @(posedge clock_pluse)
begin
if(rxd_start_reg == 1'b0)
begin
rxd_start_reg = 1'b1;
count_reg = 4'h0;
bit_cnt = 4'h0;
end
else
begin
count_reg = count_reg + 1;
if(count_reg == 4'h2)
bit_collect = rxd;
if(count_reg == 4'h3)
bit_collect = rxd;
if(count_reg == 4'h4)
begin
bit_collect = rxd;//bit_cnt
t_b = 1;//就是这里，不知道为什么编译通不过。
//(bit_collect & bit_collect) |
//(bit_collect & bit_collect) |
//(bit_collect & bit_collect) ;
bit_cnt=bit_cnt+1;
if( bit_cnt == 4'h1 && t_b == 1'b1 )
begin
rxd_start_reg = 1'b0;
end
end
if( count_reg == 5'h4 )
count_reg = 0;
if( bit_cnt > 4'h9)
begin
rxd_end = 1;
rxd_start_reg = 0;
end
end
end
assign ledout = t_b;
//assign ledout = t_b;
endmodule
/*
t_b = 1;这里就是通不过，提示Error：Node ‘221.in’missing source这样的错误提示N多。
如果修改为t_b = 1,整个编译就通过了。
请大侠帮忙。。谢谢。
*/ 位数不对？
改t_b = 1'b1试试？
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